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ADS8319IDRCR Arkusz danych(PDF) 6 Page - Texas Instruments |
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ADS8319IDRCR Arkusz danych(HTML) 6 Page - Texas Instruments |
6 / 30 page TIMING REQUIREMENTS 20pF 1.4V Iol Ioh 500µA 500µA From SDO 0.8V 2V t D ELA Y 0.3 VBD t D ELA Y 0.7 VBD 2V 0.8V ADS8319 SLAS600 – MAY 2008 ........................................................................................................................................................................................................ www.ti.com All specifications typical at –40°C to 85°C, +VA = 5 V, +4.5 V > +VBD ≥ 2.375 V PARAMETER REF FIGURE MIN TYP MAX UNIT SAMPLING AND CONVERSION RELATED tacq Acquisition time 600 ns Figure 46, Figure 48, Figure 50, tcnv Conversion time 1400 ns Figure 52 tcyc Time between conversions 2000 ns t1 Pulse width CONVST high Figure 46, Figure 48 10 ns t6 Pulse width CONVST low Figure 50, Figure 52, Figure 54 20 ns I/O RELATED tclk SCLK period 30 ns tclkl SCLK low time 13 ns Figure 46, Figure 48, Figure 50, tclkh SCLK high time 13 ns Figure 52, Figure 54, Figure 56 t2 SCLK falling edge to data remains valid 5 ns t3 SCLK falling edge to next data valid delay 24 ns ten CONVST or SDI low to MSB valid Figure 46, Figure 50 22 ns CONVST or SDI high or last SCLK falling edge to SDO Figure 46, Figure 48, Figure 50, tdis 15 ns 3-state (CS mode) Figure 52 t4 SDI valid setup time to CONVST rising edge 5 ns Figure 50, Figure 52 t5 SDI valid hold time from CONVST rising edge 5 ns t7 SCLK valid setup time to CONVST rising edge 5 ns Figure 54 t8 SCLK valid hold time from CONVST rising edge 5 ns Figure 1. Load Circuit for Digital Interface Timing Figure 2. Voltage Levels for Timing 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): ADS8319 |
Podobny numer części - ADS8319IDRCR |
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Podobny opis - ADS8319IDRCR |
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