74LVT573_4

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 — 15 September 2008

8 of 16

NXP Semiconductors

74LVT573

3.3 V octal D-type transparent latch; (3-state)

11. Waveforms

Measurement points are given in Table 8.

Measurement points are given in Table 8.

Fig 6.

Propagation delays latch enable input (LE) to

output (Qn), and latch enable (LE) pulse width

Fig 7.

Propagation delay data input (Dn) to

output (Qn)

Measurement points are given in Table 8.

with the output load.

Measurement points are given in Table 8.

Fig 8.

Output enable time to HIGH-state and output

disable time from HIGH-state

Fig 9.

Output enable time to LOW-state and output

disable time from LOW-state

Measurement points are given in Table 8.

Remark: The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig 10. Data setup and hold times for data (Dn) and latch enable (LE) inputs

001aai743

LE input

Qn output

0 V

001aai742

Dn input

Qn output

0 V

Qn output

001aai745

OE input

0 V

0 V

001aai746

Qn output

OE input

3.0 V

0 V

001aai744

0 V

0 V

LE input

Dn input

Table 8.

Measurement points

Input

Output

1.5 V

1.5 V