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ML2724DH Arkusz danych(PDF) 11 Page - Micro Linear Corporation |
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ML2724DH Arkusz danych(HTML) 11 Page - Micro Linear Corporation |
11 / 26 page ML2724 DS2724-F-03 FINAL DATASHEET DECEMBER 2005 11 15 VTUNE I VCO Tuning Voltage input from the PLL loop filter. This pin is very sensitive to noise coupling and leakage currents. 24 VSS VCCA 3.7k 15 VTUNE 8 1.25V 26 VBG O Bandgap Decouple Voltage. Decoupled to ground with a 220nF capacitor. N/A 28 RSSI O Buffered Analog RSSI output with a nominal sensitivity of 35mV/dB. In analog test modes, this pin and the AOUT output become test access points controlled by the serial control bus. 24 VSS VCCA 100 Ω 28 RSSI 8 TPI MUX RSSI MUX RSSI OP AMP SERIAL BUS SIGNALS 4 EN I (CMOS) Control Bus Enable. Enable pin for the three-wire serial control bus that sets the operating frequency and programmable options. The control registers are loaded on a low-to-high transition of the signal. Serial control bus data is ignored when this signal is high. This is a CMOS input, and the thresholds are referenced to VDD and VSS. 5 DATA I (CMOS) Serial Control Bus Data. 16-bit words, which include programming data and the two-bit address of a control, register. This is a CMOS input, and the thresholds are referenced to VDD and VSS. 6 CLK I (CMOS) Serial control bus data is clocked in on the rising edge when EN is low. This is a CMOS input; the thresholds are referenced to VDD and VSS. 31 VSS VDD 5.5k 4 EN 8 1.7p 5 DATA 6 CLK |
Podobny numer części - ML2724DH |
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Podobny opis - ML2724DH |
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