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CDCE18005 Arkusz danych(PDF) 4 Page - Texas Instruments |
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CDCE18005 Arkusz danych(HTML) 4 Page - Texas Instruments |
4 / 58 page FUNCTIONAL DESCRIPTION Output Divider0 U0P U0N U1P U1N U2P U2N U3P U3N U4P U4N AUX OUT PRI_IN SEC_IN XTAL / AUX_IN EEPROM Interface & Control /Power_Down /SYNC SPI_LE SPI_CLK SPI_MISO SPI_MOSI Output Divider1 Output Divider2 Output Divider3 Output Divider4 CDCE18005 SCAS863 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com Figure 3. CDCE18005 Block Diagram The CDCE18005 comprises three primary blocks: the interface and control block, the input block and the output block. In order to determine which settings are appropriate for any specific combination of input/output frequencies, a basic understanding of these blocks is required. The interface and control block determines the state of the CDCE18005 at power-up based on the contents of the on-board EEPROM. In addition to the EEPROM, the SPI port is available to configure the CDCE18005 by writing directly to the device registers after power-up. The input block buffers three clock signals, converts them to differential signals, and drives them onto an internal clock distribution bus. The output block provides five separate clock channels that are fully programmable and configurable to select and condition one of four internal clock sources NOTE: This Section of the data sheet provides a high-level description of the features of the CDCE18005 for purpose of understanding its capabilities. For a complete description of device registers and I/O, please refer to the Device Configuration Section. 4 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s) :CDCE18005 |
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