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TL28L92 Arkusz danych(PDF) 5 Page - Texas Instruments |
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TL28L92 Arkusz danych(HTML) 5 Page - Texas Instruments |
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5 / 61 page  1 General Description 1.1 Features 1.2 Description TL28L92 3.3-V/5-V Dual Universal Asynchronous Receiver/Transmitter www.ti.com SLLS890A – AUGUST 2008 – REVISED OCTOBER 2008 • SC28L92 Pin Compatible • Multi-Function 7-Bit Input Port (Includes IACKN) • 3.3 V to 5.0 V, –40°C to 85°C and 68xxx or – Can Serve as Clock or Control Inputs 80xxx Bus Interface – Change of State Detection on Four Inputs • Dual Full-Duplex Independent Asynchronous Inputs Have Typically > 100 k Ω Pullup Receiver/Transmitters 16 Character FIFOs for Resistors Each Receiver and Transmitter – Change of State Detectors for Modem • Pin Programming Selects 68xxx or 80xxx Bus Control Interface • Multi-Function 8-Bit Output Port • Programmable Data Format – Individual Bit Set/Reset Capability – 5 Data to 8 Data Bits Plus Parity – Outputs Can Be Programmed to Be – Odd, Even, No Parity or Force Parity Status/Interrupt Signals – 1 Stop, 1.5 Stop or 2 Stop Bits – FIFO Status for DMA Interface Programmable in 1/16-Bit Increments • Versatile Interrupt System • 16-Bit Programmable Counter/Timer – Single Interrupt Output With Eight • Programmable Baud Rate for Each Receiver Maskable Interrupting Conditions and Transmitter Selectable From: – Output Port Can be Configured to Provide a Total of up to Five Separate Interrupt – 28 Fixed Rates: 50 Bd to 230.4 kBd Outputs That May be Wire ORed – Other Baud Rates to 1 MHz at 16 × – Each FIFO Can be Programmed for Four – Programmable User-Defined Rates Derived Different Interrupt Levels From a Programmable Counter/Timer – Watchdog Timer for Each Receiver – External 1 × or 16× Clock • Maximum Data Transfer Rates: 1× – 1 Mbit/s, • Parity, Framing, and Overrun Error Detection 16 × – 1 Mbit/s • False Start Bit Detection • Automatic Wake-Up Mode for Multi-Drop • Line Break Detection and Generation Applications • Programmable Channel Mode • Start-End Break Interrupt/Status – Normal (Full-Duplex) • Detects Break Which Originates in the Middle – Automatic Echo of a Character – Local Loopback • On-Chip Crystal Oscillator – Remote Loopback • Powerdown Mode – Multi-Drop Mode (Also Called Wake-Up or 9-Bit) • Receiver Time-Out Mode • Single 3.3 V or 5 V Power Supply • Powers up to Emulate SC26C92 • Meets or Exceeds JEDEC 14C ESD Requirements The TL28L92 is a pin and function replacement for the SC26C92 operating at 3.3 V or 5 V supply with added features and deeper FIFOs. Its configuration on power-up is that of the SC26C92. Its differences from the SC26C92 are: 16 character receiver, 16 character transmit FIFOs, watchdog timer for each receiver, mode register 0 is added, extended baud rate and overall faster speeds, programmable receiver and transmitter interrupts. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. PRODUCTION DATA information is current as of publication date. Copyright © 2008–2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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