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TC7109ACPL Arkusz danych(PDF) 8 Page - TelCom Semiconductor, Inc |
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TC7109ACPL Arkusz danych(HTML) 8 Page - TelCom Semiconductor, Inc |
8 / 21 page 3-98 TELCOM SEMICONDUCTOR, INC. TC7109 TC7109A 12-BIT µP-COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS reference for (+) or (–) input voltages will cause a roll-over error. This error can be held to less than 0.5 count worst case by using a large reference capacitor in comparison to the stray capacitance. To minimize roll-over error from these sources, keep the reference common-mode voltage near or at analog common. Digital Section The digital section is shown in the block diagram (Fig- ure 4) and includes the clock oscillator and scaling circuit, a 12-bit binary counter with output latches and TTL com- patible three-state output drivers, UART handshake logic, polarity, overrange, and control logic. Logic levels are re- ferred to as LOW or HIGH. Inputs driven from TTL gates should have 3 k Ω to 5 kΩ pull-up resistors added for maximum noise immunity. For minimum power consumption, all inputs should swing from GND (LOW) to V+ (HIGH). STATUS Output During a conversion cycle, the STATUS output goes HIGH at the beginning of signal integrate and goes LOW one-half clock period after new data from the conversion has been stored in the output latches (see Figure 3). The signal may be used as a "data valid" flag to drive interrupts, or for monitoring the status of the converter. (Data will not change while status is LOW.) MODE Input The output mode of the converter is controlled by the MODE input. The converter is in its "direct" output mode, when the MODE input is LOW or left open. The output data is directly accessible under the control of the chip and byte enable inputs (this input is provided with a pull-down resistor to ensure a LOW Level when the pin is left open). When the MODE input is pulsed high, the converter enters the UART handshake mode and outputs the data in 2 bytes, then returns to "direct" mode. When the MODE input is kept HIGH, the converter will output data in the handshake mode at the end of every conversion cycle. With MODE = 0 (direct bus transfer), the send input should be tied to V+. (See "Handshake Mode.") RUN/HOLD Input With the RUN/HOLD input high, or open, the circuit operates normally as a dual-slope ADC, as shown in Figure 3. Conversion cycles operate continuously with the output latches updated after zero crossing in the deintegrate mode. An internal pull-up resistor is provided to ensure a HIGH level with an open input. Zero-Integrator Phase The ZI phase only occurs when an input overrange condition exists. The function of the ZI phase is to eliminate residual charge on the integrator capacitor after an overrange measurement. Unless removed, the residual charge will be transferred to the auto-zero capacitor and cause an error in the succeeding conversion. The ZI phase virtually eliminates hysteresis or "cross talk" in multiplexed systems. An overrange input on one channel will not cause an error on the next channel mea- sured. This feature is especially useful in thermocouple measurements, where unused (or broken thermocouple) inputs are pulled to the positive supply rail. During ZI, the reference capacitor is charged to the reference voltage. The signal inputs are disconnected from the buffer and integrator. The comparator output is con- nected to the buffer input, causing the integrator output to be driven rapidly to 0V (Figure 3). The ZI phase only occurs following an overrange and lasts for a maximum of 1024 clock periods. Differential Input The TC7109A has been optimized for operation with analog common near digital ground. With +5V and –5V power supplies, a full ±4V full-scale integrator swing maxi- mizes the analog section's performance. A typical CMRR of 86 dB is achieved for input differential voltages anywhere within the typical common-mode range of 1V below the positive supply to 1.5V above the negative supply. However, for optimum performance, the IN HI and IN LO inputs should not come within 2V of either supply rail. Since the integrator also swings with the common-mode voltage, care must be exercised to ensure the integrator output does not saturate. A worst-case condition is near a full-scale negative differential input voltage with a large positive common-mode voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common-mode voltage. In such cases, the integrator swing can be reduced to less than the recommended ±4V full-scale value, with some loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. Roll-over voltage is the main source of common-mode error, caused by the reference capacitor losing or gaining charge due to stray capacity on its nodes. With a large common-mode voltage, the reference capacitor can gain charge (increase voltage) when called upon to deintegrate a positive signal and lose charge (decrease voltage) when called upon to deintegrate a negative input signal. This difference in |
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