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U6081B Datasheet(Arkusz danych) 2 Page - TEMIC Semiconductors

Numer części U6081B
Szczegółowy opis  PWM Power Control with Low Duty Cycle Switch Off
Pobierz  8 Pages
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Producent  TEMIC [TEMIC Semiconductors]
Strona internetowa  http://www.temic.de
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U6081B
TELEFUNKEN Semiconductors
Rev. A1, 14-Feb-97
2 (8)
Pin Description
1
2
3
4
5
6
7
8
95 9944
VS
GND
VI
Osc
Output
Sense
2 VS
Delay
Pin
Symbol
Function
1
VS
Supply voltage VS
2
GND
IC ground
3
VI
Control input (duty cycle)
4
Osc
Oscillator
5
Delay
Short circuit protection delay
6
Sense
Current sensing
7
2 VS
Voltage doubler
8
Output
Output
Functional Description
Pin 1, Supply Voltage, Vs or VBatt
Overvoltage Detection
Stage 1:
If VBatt > 20 V occurs the external transistor will be
switched off and switched on again at VBatt < 18.5 V
(hysteresis).
Stage 2:
If VBatt > 28 V, the external transistor is switched on again
(load-dump protection). At the same time the voltage li-
mitation of the IC is reduced from VS ≈ 26 V to VS ≈ 20 V.
This leads to a hysteresis characteristic so that the load-
dump detection is switched off again only at VBatt < 23 V.
In this case the short–circuit protection is not in operation.
Undervoltage Detection
In the event of voltages of approximately VBatt < 5.0 V,
the external FET is switched off and the latch for short-
circuit detection is reset.
A hysteresis ensures that the FET is switched on again at
approximately VBatt
 5.4 V.
Pin 2, GND
Ground-Wire Breakage
To protect the FET in the case of ground-wire breakage,
a 820-k
W resistor between gate and source is recom-
mended to provide proper switch-off conditions.
Pin 3, Control Input
The pulse width is controlled by means of an external
potentiometer (47 k
W). The characteristic (angle of
rotation/duty cycle) is linear. The duty cycle can be varied
from 0 to 100%. To avoid inadmissibly high filament cold
currents, the dimmer is switched off at duty cycles of
approximately < 10% or is switched on only at duty
cycles of approximately > 13% (hysteresis). It is possible
to further restrict the duty cycle with the resistors R1 and
R2 (see figure 2). Pin 3 is protected against short-circuit
to VBatt and ground GND (VBatt x 16.5 V).
Output Slope Control
The rise and fall time (tr, tf) of the lamp voltage can be
limited to reduce radio interference. This is done with an
integrator which controls a power MOSFET as source
follower. The slope time is controlled by an external
capacitor C4 and the oscillator current (see figure 2).
Calculation:
t
f
+ t
r
+ V
Batt
C
4
Iosc
With VBatt = 12 V, C4 = 470 pF and Iosc = 40
mA, we thus
obtain a controlled slope of
t
f
+ t
r
+ 12 V
470 pF
40
mA +
141
ms
A 100-
W resistor in series to C4 is recomended to damp
device oscillations (see figure 2).
Pin 4, Oscillator
The oscillator determines the frequency of the output
voltage. This is defined by an external capacitor, C2. It is
charged with a constant current, I, until the upper
switching threshold is reached. A second current source
is then activated which taps a double current, 2
I, from
the charging current. The capacitor, C2, is thus discharged
by the current, I, until the lower switching threshold is
reached. The second source is then switched off again and
the procedure starts again.
Example for oscillator frequency calculation:
V
T100
+ V
S
a
1
+ (V
Batt
* I
S
R
3)
a
1
V
T
¦100 + VS
a
2
+ (V
Batt
* I
S
R
3)
a
2
V
TL
+ V
S
a
3
+ (V
Batt
* I
S
R
3)
a
3
where




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