Zakładka z wyszukiwarką danych komponentów
  Polish  ▼
ALLDATASHEET.PL

X  

ADSP-21061KS-200 Arkusz danych(PDF) 9 Page - Analog Devices

Numer części ADSP-21061KS-200
Szczegółowy opis  DSP Microcomputer Family
Download  47 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Producent  AD [Analog Devices]
Strona internetowa  http://www.analog.com
Logo AD - Analog Devices

ADSP-21061KS-200 Arkusz danych(HTML) 9 Page - Analog Devices

Back Button ADSP-21061KS-200 Datasheet HTML 5Page - Analog Devices ADSP-21061KS-200 Datasheet HTML 6Page - Analog Devices ADSP-21061KS-200 Datasheet HTML 7Page - Analog Devices ADSP-21061KS-200 Datasheet HTML 8Page - Analog Devices ADSP-21061KS-200 Datasheet HTML 9Page - Analog Devices ADSP-21061KS-200 Datasheet HTML 10Page - Analog Devices ADSP-21061KS-200 Datasheet HTML 11Page - Analog Devices ADSP-21061KS-200 Datasheet HTML 12Page - Analog Devices ADSP-21061KS-200 Datasheet HTML 13Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 47 page
background image
ADSP-21061/ADSP-21061L
–9–
REV. B
PIN DESCRIPTIONS
ADSP-21061 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for
TRST).
Unused inputs should be tied or pulled to IVDD or IGND,
except for ADDR31-0, DATA47-0, FLAG3-0, SW and inputs that
have internal pull-up or pull-down resistors (
CPA, ACK, DTx,
DRx, TCLKx, RCLKx, TMS and TDI)—these pins can be left
floating. These pins have a logic-level hold circuit that prevents
the input from floating internally.
I = Input
S = Synchronous
P = Power Supply
(O/D) = Open Drain
O = Output
A = Asynchronous
G = Ground
(A/D) = Active Drive
T = Three-State (when
SBTS is asserted, or when the
ADSP-2106x is a bus slave)
PIN FUNCTION DESCRIPTIONS
Pin
Type
Function
ADDR31-0
I/O/T
External Bus Address. The ADSP-21061 outputs addresses for external memory and peripherals
on these pins. In a multiprocessor system the bus master outputs addresses for read/writes of the
internal memory or IOP registers of other ADSP-2106xs. The ADSP-21061 inputs addresses when a
host processor or multiprocessing bus master is reading or writing its internal memory or IOP registers.
DATA47-0
I/O/T
External Bus Data. The ADSP-21061 inputs and outputs data and instructions on these pins.
The external data bus transfers 32-bit single-precision floating-point data and 32-bit fixed-point
data over Bits 47-16. 40-bit extended-precision floating-point data is transferred over Bits 47-8 of
the bus. 16-bit short word data is transferred over Bits 31-16 of the bus. Pull-up resistors on un-
used DATA pins are not necessary.
MS
3-0
O/T
Memory Select Lines. These lines are asserted (low) as chip selects for the corresponding banks
of external memory. Memory bank size must be defined in the ADSP-21061’s system control regis-
ter (SYSCON). The
MS
3-0 lines are decoded memory address lines that change at the same time as
the other address lines. When no external memory access is occurring the
MS
3-0 lines are inactive;
they are active, however, when a conditional memory access instruction is executed, whether or not the
condition is true.
MS
0 can be used with the PAGE signal to implement a bank of DRAM memory
(Bank 0). In a multiprocessor system the
MS
3-0 lines are output by the bus master.
RD
I/O/T
Memory Read Strobe. This pin is asserted (low) when the ADSP-21061 reads from external
memory devices or from the internal memory of other ADSP-21061s. External devices (including
other ADSP-21061s) must assert
RD to read from the ADSP-21061’s internal memory. In a multi-
processor system
RD is output by the bus master and is input by all other ADSP-21061s.
WR
I/O/T
Memory Write Strobe. This pin is asserted (low) when the ADSP-21061 writes to external memory
devices or to the internal memory of other ADSP-21061s. External devices must assert
WR to write to
the ADSP-21061’s internal memory. In a multiprocessor system
WR is output by the bus master and is
input by all other ADSP-21061s.
PAGE
O/T
DRAM Page Boundary. The ADSP-21061 asserts this pin to signal that an external DRAM page
boundary has been crossed. DRAM page size must be defined in the ADSP-21061’s memory con-
trol register (WAIT). DRAM can only be implemented in external memory Bank 0; the PAGE
signal can only be activated for Bank 0 accesses. In a multiprocessor system PAGE is output by the
bus master.
ADRCLK
O/T
Address Clock for synchronous external memories. Addresses on ADDR31-0 are valid before the
rising edge of ADRCLK. In a multiprocessing system ADRCLK is output by the bus master.
SW
I/O/T
Synchronous Write Select. This signal is used to interface the ADSP-2106x to synchronous memory
devices (including other ADSP-21061s). The ADSP-21061 asserts
SW (low) to provide an early indica-
tion of an impending write cycle, which can be aborted if
WR is not later asserted (e.g. in a conditional
write instruction). In a multiprocessor system,
SW is output by the bus master and is input by all other
ADSP-21061s to determine if the multiprocessor memory access is a read or write.
SW is asserted at the
same time as the address output. A host processor using synchronous writes must assert this pin when
writing to the ADSP-21061(s).
ACK
I/O/S
Memory Acknowledge. External devices can deassert ACK (low) to add wait states to an external
memory access. ACK is used by I/O devices, memory controllers or other peripherals to hold off
completion of an external memory access. The ADSP-21061 deasserts ACK as an output to add
wait states to a synchronous access of its internal memory. In a multiprocessor system, a slave
ADSP-21061 deasserts the bus master’s ACK input to add wait state(s) to an access of its internal
memory. The bus master has a keeper latch on its ACK pin that maintains the input at the level it
was last driven to.


Podobny numer części - ADSP-21061KS-200

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Analog Devices
ADSP-21061KS-200 AD-ADSP-21061KS-200 Datasheet
870Kb / 52P
   Commercial Grade SHARC DSP Microcomputer
REV. D
More results

Podobny opis - ADSP-21061KS-200

ProducentNumer częściArkusz danychSzczegółowy opis
logo
Analog Devices
ADSP21062 AD-ADSP21062 Datasheet
338Kb / 48P
   DSP Microcomputer Family
REV. B
ADSP-21060C AD-ADSP-21060C Datasheet
478Kb / 48P
   ADSP-21060 Industrial SHARC DSP Microcomputer Family
REV. B
ADSP-21060LCW-133 AD-ADSP-21060LCW-133 Datasheet
479Kb / 48P
   ADSP-21060 Industrial SHARC DSP Microcomputer Family
REV. B
ADSP-2185L AD-ADSP-2185L Datasheet
223Kb / 31P
   DSP Microcomputer
ADSP-2186M AD-ADSP-2186M Datasheet
288Kb / 40P
   DSP Microcomputer
REV. 0
ADSP-2183 AD-ADSP-2183 Datasheet
252Kb / 31P
   DSP Microcomputer
REV. C
ADSP-2184 AD-ADSP-2184 Datasheet
213Kb / 31P
   DSP Microcomputer
REV. 0
ADSP-2184L AD-ADSP-2184L Datasheet
216Kb / 31P
   DSP Microcomputer
REV. 0
ADSP-2184 AD-ADSP-2184_15 Datasheet
216Kb / 31P
   DSP Microcomputer
REV. 0
ADSP-2185 AD-ADSP-2185_15 Datasheet
291Kb / 32P
   DSP Microcomputer
REV. 0
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47


Arkusz danych Pobierz

Go To PDF Page


Link URL




Polityka prywatności
ALLDATASHEET.PL
Czy Alldatasheet okazała się pomocna?  [ DONATE ] 

O Alldatasheet   |   Reklama   |   Kontakt   |   Polityka prywatności   |   Linki   |   Lista producentów
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com