6

FIGURE 1. THREE-STATE PROPAGATION DELAY WAVEFORMS AND TEST CIRCUIT

FIGURE 2. PROPAGATION DELAY TIMES AND TEST CIRCUIT

DUT

WITH

THREE-

STATE

OUTPUT

INPUT LEVEL

90%

10%

GND

OUTPUTS

ENABLED

OUTPUTS

DISABLED

OUTPUT: LOW

TO OFF TO LOW

OUTPUT: HIGH

TO OFF TO HIGH

OTHER

INPUTS

(TIED HIGH

OR LOW)

OUTPUT

DISABLE

50pF

500

500

OUT

OUTPUTS

ENABLED

(OPEN DRAIN)

OUTPUT

DISABLE

I OR S

E

OUTPUT Y

90%

10%

DUT

OUTPUT

OUTPUT

LOAD

500

Ω

50pF

FIGURE 3. PROPAGATION DELAY TIMES

CD74AC

CD74ACT

Input Level

3V

1.5V

CD74AC153, CD74ACT153