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CDC2582 Arkusz danych(PDF) 5 Page - Texas Instruments |
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CDC2582 Arkusz danych(HTML) 5 Page - Texas Instruments |
5 / 10 page CDC2582 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH DIFFERENTIAL LVPECL CLOCK INPUTS SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION CLKIN CLKIN 44, 45 I Clock input. CLKIN and CLKIN are the differential clock signals to be distributed by the CDC2582 clock-driver circuit. These inputs are used to provide the reference signal to the integrated PLL that generates the clock-output signals. CLKIN and CLKIN must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and valid CLKIN and CLKIN signals are applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. CLR 40 I Clear. CLR is used to reset the VCO/4 reference frequency. CLR is negative-edge triggered and should be strapped to VCC or GND for normal operation. FBIN 48 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of the twelve clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to obtain zero-phase delay between the FBIN and the differential clock input (CLKIN and CLKIN). OE 42 I Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE is high, all outputs are in the high-impedance state. Since the feedback signal for the PLL is taken directly from an output terminal, placing the outputs in the high-impedance state interrupts the feedback loop; therefore, when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is required before the PLL obtains phase lock. SEL1, SEL0 51, 50 I Output configuration select. SEL0 and SEL1 select the output configuration for each output bank (e.g., 1 ×, 1/2×, or 2×) (see Tables 1 and 2). TEST 41 I TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST is low, all outputs operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses the PLL circuitry. TEST should be strapped to GND for normal operation. 1Y1 – 1Y3 2Y1 – 2Y3 3Y1 – 3Y3 2, 5, 8 12, 15, 18 22, 25, 28 O These outputs are configured by SEL1 and SEL0 to transmit one-half or one-fourth the frequency of the VCO. The relationship between the input clock frequency and the output frequency is dependent on SEL1 and SEL0 and the frequency of the output being fed back to FBIN. The duty cycle of the Y outputs is nominally 50% independent of the duty cycle of the input clock signals. Each output has an internal series resistor to dampen transmission-line effects and improve the signal integrity at the load. 4Y1 – 4Y3 32, 35, 38 O These outputs transmit one-half the frequency of the VCO. The relationship between the input clock frequency and the output frequency is dependent on the frequency of the output being fed back to FBIN. The duty cycle of the Y outputs is nominally 50% independent of the duty cycle of CLKIN. Each output has an internal series resistor to dampen transmission-line effects and improve the signal integrity at the load. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC – 0.5 V to 4.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input voltage range, VI (see Note 1) – 0.5 V to 7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage range applied to any output in the high state or power-off state, VO (see Note 1) – 0.5 V to 5.5 V . . . Current into any output in the low state, IO 24 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input clamp current, IIK (VI < 0) – 20 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current, IOK (VO < 0) – 50 mA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum power dissipation at TA = 55°C (in still air) (see Note 2) 1.2 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Storage temperature range, Tstg –65 °C to 150°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150 °C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. |
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Podobny opis - CDC2582 |
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