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CDC921DL Arkusz danych(PDF) 1 Page - Texas Instruments |
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CDC921DL Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 17 page CDC921 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS623 –MAY 27, 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Generates Clocks for Pentium™ III Class Microprocessors D Supports a Single Pentium III Microprocessor D Uses a 14.318 MHz Crystal Input to Generate Multiple Output Frequencies D Includes Spread Spectrum Clocking (SSC), 0.5% Downspread for Reduced EMI Performance D Power Management Control Terminals D Low Output Skew and Jitter for Clock Distribution D Operates from Dual 2.5-V and 3.3-V Supplies D Generates the Following Clocks: – 3 CPU (2.5 V, 100/133 MHz) – 10 PCI (3.3 V, 33.3 MHz) – 1 CPU/2 (2.5 V, 50/66 MHz) – 1 APIC (2.5 V, 16.67 MHz) – 3 3V66 (3.3 V, 66 MHz) – 2 REF (3.3 V, 14.318 MHz) – 1 48MHz (3.3 V, 48 MHz) D Packaged in 48-Pin SSOP Package D Designed for Use with TI’s Direct Rambus™ Clock Generators (CDCR81, CDCR82, CDCR83) description The CDC921 is a clock synthesizer/driver that generates CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF system clock signals to support computer systems with a single Pentium III class microprocessor. All output frequencies are generated from a 14.318-MHz crystal input. Instead of a crystal, a reference clock input can be provided at the XIN input. Two phase-locked loops (PLLs) are used to generate the host frequencies and the 48-MHz clock frequency. On-chip loop filters and internal feedback eliminate the need for external components. The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100. The 48MHz clock can be independently disabled via the control inputs SEL0, SEL1, and SEL133/100. In this state, the 48-MHz PLL is disabled and the 48MHz clock is driven to high impedance to reduce component jitter. The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely with the outputs in a low-level output state. Copyright © 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0 REF1 VDD3.3V XIN XOUT GND PCI0 PCI1 VDD3.3V PCI2 PCI3 PCI4 PCI5 GND PCI6 PCI7 VDD3.3V PCI8 PCI9 GND 3V66(0) 3V66(1) 3V66(2) VDD3.3V GND VDD2.5V APIC GND VDD2.5V CPU_DIV2 GND VDD2.5V CPU2 GND VDD2.5V CPU1 CPU0 GND VDD3.3V GND PWR_DWN SPREAD SEL1 SEL0 VDD3.3V 48MHz GND SEL133/100 DL PACKAGE (TOP VIEW) Intel and Pentium III are trademarks of Intel Corporation. Direct Rambus and Rambus are trademarks of Rambus Inc. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. |
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