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SN74ABT18652PM Arkusz danych(PDF) 1 Page - Texas Instruments |
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SN74ABT18652PM Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 11 page SN54ABT18652, SN74ABT18652 SCAN TEST DEVICES WITH 18-BIT BUS TRANSCEIVERS AND REGISTERS SCBS132A – AUGUST 1992 – REVISED OCTOBER 1992 Copyright © 1992, Texas Instruments Incorporated 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 • Members of the Texas Instruments SCOPE ™ Family of Testability Products • Members of the Texas Instruments Widebus ™ Family • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture • Include D-Type Flip-Flops and Control Circuitry to Provide Multiplexed Transmission of Stored and Real-Time Data • Two Boundary-Scan Cells per I/O for Greater Flexibility • State-of-the-Art EPIC-ΙΙB ™ BiCMOS Design Significantly Reduces Power Dissipation • SCOPE ™ Instruction Set – IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, and P1149.1A CLAMP and HIGHZ – Parallel Signature Analysis at Inputs With Masking Option – Pseudo-Random Pattern Generation From Outputs – Sample Inputs/Toggle Outputs – Binary Count From Outputs – Device Identification – Even-Parity Opcodes • Packaged in 64-Pin Plastic Shrink Quad Flat Pack (PM) and 68-Pin Ceramic Quad Flat Pack (HV) 1B4 1B5 1B6 GND 1B7 1B8 1B9 VCC NC 2B1 2B2 2B3 2B4 GND 2B5 2B6 2B7 1A3 1A4 1A5 GND 1A6 1A7 1A8 1A9 NC VCC 2A1 2A2 2A3 GND 2A4 2A5 2A6 19 20 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 22 23 24 25 67 66 65 64 63 68 62 60 59 58 61 26 27 28 29 30 57 56 18 55 54 53 52 31 32 33 34 SN54ABT18652 . . . HV PACKAGE (TOP VIEW) NC – No internal connection PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
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