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ADC-207LM Arkusz danych(PDF) 2 Page - Murata Power Solutions Inc. |
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ADC-207LM Arkusz danych(HTML) 2 Page - Murata Power Solutions Inc. |
2 / 6 page PHYSICAL/ENVIRONMENTAL PARAMETERS MIN. TYP. MAX. UNITS Operating Temp. Range, Case: LC/MC Versions 0 — +70 °C MM/LM/QL Versions –55 — +125 °C Storage Temp. Range –65 — +150 °C Package Type DIP 18-pin ceramic DIP LCC 24-pin ceramic LCC Functional Specifications (Typical at +5V power, +25°C, 20MHz clock, +REFERENCE = +5V, –REFERENCE = ground, unless noted) ANALOG INPUT MIN. TYP. MAX. UNITS Input Type Single-ended, non-isolated Input Range (dc-20MHz) 0 — +5 Volts Input Impedance — 1000 — Ohms Input Capacitance (Full Range) — 10 — pF DIGITAL INPUTS Logic Levels Logic "1" +3.2 — — Volts Logic "0" — — +0.8 Volts Logic Loading "1" — ±1 ±5 microamps Logic Loading "0" — ±1 ±5 microamps Sample Pulse Width (During Sampling Portion of Clock) 12 — — ns Reference Ladder Resistance 225 330 — Ohms PERFORMANCE Conversion Rate ➀ 20 25 — MHz Harmonic Distortion ➁ (8MHz 2nd Order Harmonic) — –40 — dB Differential Gain ➂ — 3 — % Differential Phase ➂ — 1.5 — degrees Aperture Delay — 8 — ns Aperture Jitter — 50 — ps No Missing Codes LC/MC grade 0 — +70 °C LM/MM grade –55 — +125 °C Integral Linearity ➃ — ±0.8 ±1 LSB Over Temperature Range — ±1 — LSB Differential Nonlinearity — ±0.3 ±0.5 LSB Over Temperature Range — ±0.4 ±0.6 LSB Power Supply Rejection — ±0.02 — %FSR/%Vs DIGITAL OUTPUTS Data Coding Straight binary Data Output Resolution 7 — — Bits Logic Levels Logic "1" +2.4 +4.5 — Volts Logic "0" (at 1.6mA) — — +0.4 Volts Logic Loading "1" –4 — — mA Logic Loading "0" +4 — — mA Output Data Valid Delay (From Rising Edge) — 15 17 ns POWER REQUIREMENTS Power Supply Range (+VDD) +3.0 +5.0 +5.5 Volts Power Supply Current — +50 +70 mA Power Dissipation — 250 385 mW Footnotes: ➀ At full power input and chip selects enabled. ➁ At 4MHz input and 20MHz clock. ➂ For 10-step, 40 IRE NTSC ramp test. ➃ Adjustable using reference ladder midpoint tap. See ADC-207 Operation. (MSB) 0.1µF 0.1µF 4.7µF 0.01µF +5V +15 + + –15 47µF 11 12 10 5 HA-5033 10 W +5V 20MHz CLOCK (LSB) B7 B6 B5 B4 B3 B2 B1 OF OF B1 B2 B3 B4 B5 B6 B7 +VDD CS2 CS1 +REFERENCE MID VIN –REFERENCE DIGITAL GND ANALOG GND CLOCK 18 1 2 3 4 5 6 7 8 9 0.1µF + 47µF 17 16 15 14 13 12 11 10 PARAMETERS LIMITS UNITS Power Supply Voltage (+VDD) –0.5 to +7 Volts Digital Inputs –0.5 to +5.5 Volts Analog Input –0.5 to (+VDD +0.5) Volts Reference Inputs –0.5 to +VDD Volts Digital Outputs –0.5 to +5.5 Volts (short circuit protected to ground) Lead Temperature (10 sec. max.) +300 °C ABSOLUTE MAXIMUM RATINGS Figure 2. Typical Connections for Using the ADC-207 TECHNICAL NOTES 1. Input Buffer Amplifier – Since the ADC-207 has a switched capacitor type input, the input impedance of the 207 is dependent on the clock frequency. At relatively slow conversion rates, a general purpose type input buffer can be used; at high conversion rates DATEL recommends either the HA-5033 or Elantec 2003. See Figure 2 for typical connections. 2. Reference Ladder – Adjusting the voltage at +REFERENCE adjusts the gain of the ADC-207. Adjusting the voltage at –REFERENCE adjusts the offset or zero of the ADC-207. The midpoint pin is usually bypassed to ground through a 0.1µF capacitor, although it can be tied to a precision voltage halfway between +REFERENCE and –REFERENCE. This would improve integral linearity beyond 7 bits. 3. Clock Pulse Width – To improve performance at Nyquist bandwidths, the clock duty cycle can be adjusted so that the low portion of the clock pulse is 12ns wide. The smaller aperture allows the ADC-207 to closely resemble an ideal sampler. See Figure 4. 4. At sampling rates less than 100kHz, there may be some degradation in offset and differential nonlinearity. Performance may be improved by increasing the clock duty cycle (decreasing the time spent in the sample mode). CAUTION Since the ADC-207 is a CMOS device, normal precautions against static electricity should be taken. Use ground straps, grounded mats, etc. The Absolute Maximum Ratings of the device MUST NOT BE EXCEEDED as irrevocable damage to the ADC-207 will occur. |
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