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ADC-305 Arkusz danych(PDF) 2 Page - Murata Power Solutions Inc.

Numer części ADC-305
Szczegółowy opis  8-Bit, 20MHz CMOS A/D Converters
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Producent  MURATA-PS [Murata Power Solutions Inc.]
Strona internetowa  http://www.murata-ps.com
Logo MURATA-PS - Murata Power Solutions Inc.

ADC-305 Arkusz danych(HTML) 2 Page - Murata Power Solutions Inc.

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Technical Notes
1.
The ADC-305 has separate +AVS and +DVS pins. It is recommended that both +AVS
and +DVS be powered from a single supply since a time lag between start up of separate
supplies could induce latch up. Other external logic circuits must be powered from a separate
digital supply. +DVS (pins 11 and 13) and +AVs (pins 14, 15 and 18) should be tied together
externally. DGND (pins 2 and 24) and AGND (pins 20 and 21) should also be tied together
externally. Power supply grounds must be connected at one point to the ground plane directly
beneath the device. Digital returns should not flow through analog grounds.
2.
Bypass all power lines to ground with a 0.1µF ceramic chip capacitor in parallel with a 47µF
electrolytic capacitor. Locate the bypass capacitor as close to the unit as possible.
3.
Even though the analog input capacitance is a low 15pF, it is recommended that high
frequency input be provided via a high speed buffer amplifier. A parasitic oscillation may be
generated when a high speed amplifier is used. A 75 ohm resister inserted between the output
of an amplifier and the analog input of the ADC-305 will improve the situation. A resistor larger
than 100 ohms may degrade linearity.
4.
The input voltage range is determined by voltages applied to VRB (Reference Bottom) and
VRT (Reference Top). Keep to the following equations:
0V≤VRB≤VRT≤2.8V
1.8V≤VRT–VRB≤2.8V
The analog input range is normally 2Vp-p.
Self Bias Mode
a.
Tie VRB to VRBS, and tie VRT to VRTS respectively. The analog input range in this case is
+0.64V to +2.73V nominal.
b.
Tie VRB to AGND, and tie VRT to VRTS respectively. The analog input voltage range is 0 to
+2.39V in this case. These values may differ from one device to another. Voltage changes on
the +5V supply have a direct influence on the performance of the device. The use of external
references is recommended for applications sensitive to gain error.
External Reference Mode
Tie VRB to AGND, and apply +2V to VRT to use at 0 to +2V input voltage range. The reference
resistance between VRB and VRT is about 300 ohms. It is important to make the output
impedance of the reference source small enough while, at the same time, keeping sufficient
drive capacity. Insert a 0.1µF bypass ceramic chip capacitor between VRT and GND to
minimize the effect of the 20MHz clock running nearby. See Figure 5.
5.
Logic inputs are CMOS compatible. Normally a series 74HC is used as a driver. It is
recommended to pull up to +5V if the device is driven with TTL.
6.
The start convert (A/D CLK) pulse can be a 50% duty cycle clock. Both TPW1 and TPW0 are
25ns minimum. A slightly longer TPW1 will improve linearity of the system for higher frequency
input signals.
7. The digital data outputs are 3-state and TTL compatible. To enable the 3-state
outputs, connect the OUTPUT ENABLE (pin 1) to GND. To disable, connect it to
+5V. It is recommended that the data outputs be latched and buffered through
output registers.
8. Maximum 30ns (18ns typical) after the rising edge of the Nth conversion pulse, the
result of the (N-3) conversion can be obtained. Data is stored firmly in an output
register, such as an 74LS574, using the rising edge of a start convert pulse as a
trigger. The (N–4) data is stored in this case. See the timing diagrams, Figure 2
and 4.
9. The 20MHz sampling rate is guaranteed. It is not recommended to use this device
at sampling rates slower than 500kHz because the droop characteristics of the
internal sample and holds will then exceed the limit required to maintain the
specified accuracy of the device.
Functional Specifications
(Specification are typical at TA = +25°C, +VRT = +2.5V, VRB = +0.5V, +AVS = +DVS =
+5v, fS = 20MHz sampling unless otherwise specified.)
Analog Inputs
Min.
Typ.
Max.
Units
Input Voltage Range (VIN)
+0.5 to +2.5
Volts
Input Capacitance
11
pF
(VIN = 1.5Vdc+0.07VRMS)
Input Impedance
12.5
k
Ω
Input Signal Bandwidth
18
MHz
(VIN-2Vp-p, –1dB)
REFERENCE INPUTS
Ref. Resitance
VRT to VRB
230
300
450
Ω
Ref. Current
4.5
6.6
8.7
mA
Ref. Voltage
VRT
+1.8
+2.8
Volts
VRB
0
VRT
Volts
Offset Voltage
VRT
–10
–35
–60
mV
VRB
0
+15
+45
mV
Self Bias I
➀ ➁ VRBS
+0.6
+0.64
+0.68
Volts
VRTS-VRBS
+1.96
+2.09
+2.21
Volts
Self Bias II
➀ ➂ VRTS
+2.25
+2.39
+2.53
Volts
DIGITAL INPUTS
Input Voltage (CMOS)
Logic Levels (VIH) "1"
+4
Volts
Logic Level (VIL) "0"
+1
Volts
Input Current (@VIH=+DVS)"1"
5
µA
(@VIL=0) "0"
5
µA
Clock Pulse Width TPW1
25
ns
(A/D CLK)
TPW0
25
ns
DIGITAL Outputs
Output Data
8-bit Binary Parallel
Output Voltage
3-State TTL compatible
Output Current
Logic Level "1"
–1.1
mA
Logic Level "0"
+3.7
mA
Output Current
Logic Level "1"
16
µA
Logic Level "0"
16
µA
Output Data Delay, Td
18
30
ns
PERFORMANCE
Resolution
8
Bit
Maximum Sampling Rate
20
MHz
Minimum Sampling Rate
0.5
MHz
Aperature Delay, TA
4
ns
Aperature Jitter
30
ps
Differential Linearity Error
±0.3
±0.5
LSB
Integral Linearity Error
+0.5
+1.3
LSB
Differential Gain Error
1
%
Differential Phase Error
0.5
deg
POWER REQUIREMENTS
Min.
Typ.
Max.
Units
Power Supply (+AVS, +DVS)
+4.75
+5.0
+5.25
Volts
I A GND - D GND I
100
mV
Power Supply Current
12
17
mA
Power Dissipation
60
85
mW
Physical/Environmental
Operating Temp. Range
–40 to +85°C
Storage Temp. Range
–55 to +150°C
Package Type
ADC-305-1
24-pin Plastic DIP
ADC-305-3
24-pin Plastic SOP
Weight
ADC-305-1
2.0 grams
ADC-305-3
0.3 grams
Footnotes:
➀ See Technical Note 4
➁ Short VRB (pin 23) to VRBS (pin 22).
Short VRT (pin 17) to VRTS (pin 16).
➂ Short VRB (pin 23) to A GND.
Short VRT (pin 17) to VRTS (pin 16).
➃ OE=OV, VOH=+DVS–0.5V,
VOL=+0.4V
➄ OE=+DVS, VOH=+DVS, VOL=0V
➅ NTSC 40IRE mode ramp, 14.3MHz
sampling
PARAMETERS
MIN
MAX
UNITS
Power Supply Voltage (+AVS, +DVS)
–0.5
+7
Volts
Analog Input Voltage (VIN)
–0.5
+AVS +0.5
Volts
Reference Input Voltage (VRT, VRB)
–0.5
+AVS +0.5
Volts
Digital Input Voltage (VIH, VIL)
–0.5
+DVS +0.5
Volts
Digital Output Voltage (VOH, VOL)
–0.5
+DVS +0.5
Volts
ADC-305
8-Bit, 20MHz CMOS A/D Converters
MDA_ADC-305.B01 Page 2 of 6
Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000
www.murata-ps.com


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