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Zakładka z wyszukiwarką danych komponentów |
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Zakładka z wyszukiwarką danych komponentów |
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ADC-321 Arkusz danych(PDF) 4 Page - Murata Power Solutions Inc. |
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ADC-321 Arkusz danych(HTML) 4 Page - Murata Power Solutions Inc. |
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4 / 8 page  Figure 2-1. ADC-321 Timing Diagram Figure 2-2. ADC-321 Timing Diagram VIN MSB LSB Table 2: Digital Output Coding OUTPUT CODE 0V 0 0 0 0 0 0 0 0 +7.812mV 0 0 0 0 0 0 0 1 +0.9922V 0 1 1 1 1 1 1 1 +1.000V 1 0 0 0 0 0 0 0 +1.500V 1 1 0 0 0 0 0 0 +1.9922V 1 1 1 1 1 1 1 1 THEORY OF OPERATION (See Functional Block Diagram, Figure 1, and Timing Diagrams, Figure 2) 1. The DATEL ADC-321 is a 2-step parallel A/D converter featuring a 4-bit upper comparator group and two 4-bit lower comparator groups, each with built-in sample and hold. A reference voltage equal to the voltage between (VRT – VRB)/16 is constantly applied to the 4-bit upper comparator block. A voltage corresponding to the upper data is fed through the reference supply to the lower data. VRTS and VRBS pins provde the self generation function for VRT (reference voltage top) and VRB (reference voltage bottom) voltages. 2. This converter uses an offset cancelation type comparator and operates synchronously with the external clock. It features various operating modes which are shown in the Timing Diagram (Figure 2) by the symbols S, H and C. These characters stand for Input Sampling (Auto Zero) Mode, Input Hold Mode and Comparison Mode. 3. The operation of the respective parts is as indicated in Figure 2-3. For instance, input voltage N is sampled with the falling edge of the first clock by means of the upper comparator block and the lower comparator A block. Input voltage N+1 is sampled with the falling edge of the second clock by means of the upper comparator block and lower comparator B block. The upper comparator block finalizes comparison data UD(N) with the rising edge of the second clock. The lower comparator block finalizes comparison data LD(N) with the rising edge of the third clock. UD(N) and LD(N) are combined and routed to the output as Output Data N with the rising edge of the fourth clock. Thus there is a 2.5 clock delay from the analog input sampling point to the digital data output. 1.3V tr = 4.5ns 90% 10% VOL tphz tplz 90% tr = 4.5ns 10% tpzh 1.3V 1.3V tpzl 0V 3V VOH /(=DGND) /(=DGND) VOL VOH OE INPUT OUTPUT 1 OUTPUT 2 CLOCK 1.3V tr = 4ns tf = 4ns 90% 10% DATA OUTPUTS 0. 3 DVS 0. 7 DVS tpLH 3V 0V tpHL ADC-321 8-Bit, 50MHz Video A/D Converter Technical enquiries email: sales@murata-ps.com, tel: +1 508 339 3000 www.murata-ps.com MDA_ADC-321.B01 Page 4 of 8 |
Podobny numer części - ADC-321 |
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Podobny opis - ADC-321 |
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