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TDA9951 Arkusz danych(PDF) 6 Page - NXP Semiconductors |
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TDA9951 Arkusz danych(HTML) 6 Page - NXP Semiconductors |
6 / 41 page TDA9951_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 7 August 2008 6 of 41 NXP Semiconductors TDA9951 CEC/I2C-bus translator The seven-bit I2C-bus slave address is hard-coded as 34h and can be changed to 35h by setting the pin A0, as shown in Table 3 and Table 4. This enables two TDA9951 to be connected to the same host using the addresses 34h and 35h. Alternatively, changing the address enables one TDA9951 to avoid address clashes with other I2C-bus slaves. 8.2 Configuring the TDA9951 The TDA9951 is controlled using a series of registers. The first byte of any I2C-bus write frame configures the address pointer register APR. This determines the TDA9951 register accessed by the next I2C-bus read or write. If for example, a read is carried out without first writing to the address pointer register, the register returned is the register that address pointer register was last set to. The address pointer auto-increments after each successful read or write for all address pointer values other than 00h. When the address pointer register is set 00h, the common status register is polled using successive reads without needing to reset the address pointer register each time. When the address pointer register is set higher than 07h, this is treated as setting it to 07h. This is because all message data transfers must start from register 07h and continue by auto-incrementing in one contiguous transfer. When the host writes to two or more non-contiguous registers, two separate write sequences are used with either a STOP/START sequence or repeated START between them. Before a read takes place, the host must first write to the address pointer register (if required) and then, repeat the START condition or STOP/START sequence. Finally, it starts reading data bytes until the read sequence is complete. Table 4. I2C-bus slave address Bit 7 6 5 4 3 2 1 0 Value 011010A0 R/W Table 5. I2C Register configuration Register Description Address Read/Write Reference APR Address Pointer Register 00h W Table 6 CSR Common Status Register 00h R Table 7 CER Common Error Register 01h R Table 8 CVR Common Version Register 02h R Table 9 CCR Common Control Register 03h R/W Table 10 ACKH CEC Address ACK High register 04h R/W Table 11 ACKL CEC Address ACK Low register 05h R/W Table 12 CCONR Common Configuration Register 06h R/W Table 14 CDR Common Data Registers 07h to 19h R/W Table 15 |
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