Figure 11. ADCDS-1405 Timing Diagram

Figure 10. Reference Hold Timing

which is the difference between the "held" reference level

and its associated video level. When the "CDS Output" signal

has settled to the desired accuracy (user defined), the A/D

conversion process can be initiated with the rising edge of a

single start convert (Pin 25) signal.

Once the A/D conversion has been initiated, Reference Hold

(Pin 26) can be placed back into the "Acquisition" mode in

order to begin aquiring the next reference level. For optimal

performance the ADCDS-1405's internal sample-hold

should be placed back into the "Aquisition" mode (Reference

Hold to logic "0") during the CCD's "Reference Quiet Time"

("Reference Quiet Time" is defined as the period when the

CCD's reference signal has settled from all switching transients

to the desired accuracy (see Figure 10). Placing the sample-

hold back into the "aquisition" mode during the "Reference

Quiet Time" prevents the ADCDS-1405's internal amplifiers

from unnecessarily tracking (reproducing) the large switching

transients that occur during the CCD's reset to reference

transition.

Reset N

Reset N+1

Reset N+2

Reset N+3

Reset N+4

CCD OUTPUT

CDS OUTPUT

START CONVERT

DATA OUTPUT

REFERENCE HOLD IN

CDS OUTPUT

DATA OUTPUT

100ns min.

133ns min

120ns min settling line

Full Scale

Step

DATA N-4 VALID

DATA N-3 VALID

DATA N-2 VALID

DATA N-1 VALID

DATA N VALID

20ns min

N

Ref N

Video N

Ref. N+1

Video N+1

70ns min.

200ns min.

75ns min. settling time

50ns typ.

20ns max

Ref. N

Video N

Video N+1

Ref. N+2

Video N+1

Video N+2

Ref. N+3

Video N+1

Video N+3

Ref. N+4

N+2

N+3

N+1

N+2

N+3

Hold

Acquisition

Time

N+1

Invalid data

30ns min., 50ns max.

DATA VALID

50ns typ.

N-4

N-3

N-2

N-1

CCD

OUTPUT

REFERENCE

HOLD

Note: For optimal performance (Fastest Acquisition Time), the ADCDS-1405 should be placed into the Acquisition mode (Reference Hold to logic "0")

during the CCD output's Reference "Quiet Time". Reference "Quiet Time" is defined as the period when the reference signal's switching transients

have settled to an acceptable (user defined) accuracy.

HOLD

Reset

Video

Reference

Reference

"Quiet Time"

100NS MIN.

Acquisition Time

Acquisition mode during

Reference "Quiet Time"

ADCDS-1405

14-Bit, 5 Megapixels/Second, CCD Signal Processor

www.murata-ps.com

MDC_ADCDS-1405.B02 Page 8 of 9