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SN74GTL16616DL Arkusz danych(PDF) 1 Page - Texas Instruments |
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SN74GTL16616DL Arkusz danych(HTML) 1 Page - Texas Instruments |
1 / 11 page SN54GTL16616, SN74GTL16616 17-BIT LVTTL-TO-GTL/GTL+ UNIVERSAL BUS TRANSCEIVERS WITH BUFFERED CLOCK OUTPUTS SCBS481F – JUNE 1994 – REVISED NOVEMBER 1999 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Members of the Texas Instruments Widebus ™ Family D Universal Bus Transceiver (UBT ™) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode D GTL Buffered CLKAB Signal (CLKOUT) D Translate Between GTL/GTL+ Signal Levels and LVTTL Logic Levels D Support Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs D Equivalent to ’16601 Function D Ioff Supports Partial-Power-Down Mode Operation D Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D Distributed VCC and GND-Pin Configuration Minimizes High-Speed Switching Noise D Package Options Include Plastic Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Ceramic Flat (WD) Packages description The ’GTL16616 devices are 17-bit universal bus transceivers (UBTs) that provide LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. They combine D-type flip-flops and D-type latches to allow for transparent, latched, clocked, and clocked-enabled modes of data transfer identical to the ’16601 function. Additionally, they provide for a copy of CLKAB at GTL/GTL+ signal levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic levels (CLKIN). The devices provide an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing ( <1 V), reduced input threshold levels, and output edge control (OEC ™). The user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or the preferred higher noise margin GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. VCC (5 V) supplies the internal and GTL circuitry while VCC (3.3 V) supplies the LVTTL output buffers. Copyright © 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, OEC, and UBT are trademarks of Texas Instruments Incorporated. SN54GTL16616 . . . WD PACKAGE SN74GTL16616 . . . DGG OR DL PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 OEAB LEAB A1 GND A2 A3 VCC (3.3 V) A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC (3.3 V) A16 A17 GND CLKIN OEBA LEBA CEAB CLKAB B1 GND B2 B3 VCC (5 V) B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 VREF B16 B17 GND CLKOUT CLKBA CEBA |
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