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SN74LVTH273DWR Arkusz danych(PDF) 1 Page - Texas Instruments

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Numer części SN74LVTH273DWR
Szczegółowy opis  3.3-V ABT OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
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Strona internetowa  http://www.ti.com
Logo TI - Texas Instruments

SN74LVTH273DWR Arkusz danych(HTML) 1 Page - Texas Instruments

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SN54LVTH273, SN74LVTH273
3.3V ABT OCTAL DTYPE FLIPFLOPS
WITH CLEAR
SCBS136M − MAY 1992 − REVISED OCTOBER 2003
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
D Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Support Unregulated Battery Operation
Down To 2.7 V
D Buffered Clock and Direct-Clear Inputs
D Individual Data Input to Each Flip-Flop
D Ioff Supports Partial-Power-Down-Mode
Operation
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 500 mA Per
JESD 17
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LVTH273 ...J PACKAGE
SN74LVTH273 . . . DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
SN54LVTH273 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
2D
2Q
3Q
3D
4D
8D
7D
7Q
6Q
6D
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
description/ordering information
These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D)
inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the
transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the
D-input signal has no effect at the output.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC − DW
Tube
SN74LVTH273DW
LVTH273
SOIC − DW
Tape and reel
SN74LVTH273DWR
LVTH273
−40
°C to 85°C
SOP − NS
Tape and reel
SN74LVTH273NSR
LVTH273
−40
°C to 85°C
SSOP − DB
Tape and reel
SN74LVTH273DBR
LXH273
TSSOP − PW
Tube
SN74LVTH273PW
LXH273
TSSOP − PW
Tape and reel
SN74LVTH273PWR
LXH273
−55
°C to 125°C
CDIP − J
Tube
SNJ54LVTH273J
SNJ54LVTH273J
−55
°C to 125°C
LCCC − FK
Tube
SNJ54LVTH273FK
SNJ54LVTH273FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Copyright
 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.


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