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74ALVCHR16269AGRE4 Datasheet(Arkusz danych) 1 Page - TI store

Numer części 74ALVCHR16269AGRE4
Szczegółowy opis  12-BIT TO 24-BIT REGISTERED BUS EXCHANGER WITH 3-STATE OUTPUTS
Pobierz  12 Pages
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Producent  TI [TI store]
Strona internetowa  http://www.ti.com
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FEATURES
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
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OEA
OEB1
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
NC
SEL
OEB2
CLKENA2
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
CLKENA1
CLK
NC − No internal connection
SN74ALVCHR16269A
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050O – AUGUST 1995 – REVISED SEPTEMBER 2004
Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Max tpd of 5.2 ns at 3.3 V
±24-mA Output Drive at 3.3 V
All Outputs Have Equivalent 26-
Ω Series
Resistors, So No External Resistors Are
Required
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCHR16269A is used in applications in
which two ports must be multiplexed onto, or
demultiplexed from, a single port. It is particularly
suitable
as
an
interface
between
synchronous
DRAMs and high-speed microprocessors.
Data is stored in the internal B-port registers on the
low-to-high transition of the clock (CLK) input, when
the appropriate clock-enable (CLKENA) inputs are
low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a 24-bit
word on the B port. For data transfer in the B-to-A
direction, a single storage register is provided. The select (SEL) line selects 1B or 2B data for the A outputs. The
register on the A output permits the fastest possible data transfer, thus extending the period during which the
data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK.
Data flow is controlled by the active-low output enables (OEA, OEB1, and OEB2).
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
Tube
SN74ALVCHR16269AL
SSOP – DL
ALVCHR16269A
Tape and reel
SN74ALVCHR16269ALR
-40
°C to 85°C
TSSOP – DGG
Tape and reel
SN74ALVCHR16269AGR
ALVCHR16269A
TVSOP – DGV
Tape and reel
SN74ALVCHR16269AVR
VR269A
(1)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1995–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.




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