SN74CBT3126

QUADRUPLE FET BUS SWITCH

SCDS020E – MAY 1995 – REVISED MAY 1998

1

POST OFFICE BOX 655303

Packages)

JESD 17

Small-Outline (D), Shrink Small-Outline

(DBQ), Thin Very Small-Outline (DGV), and

Thin Shrink Small-Outline (PW) Packages

description

The SN74CBT3126 quadruple FET bus switch

features independent line switches. Each switch

is disabled when the associated output-enable

(OE) input is low.

The SN74CBT3126 is characterized for operation

from –40

°C to 85°C.

FUNCTION TABLE

(each bus switch)

INPUT

OE

FUNCTION

L

Disconnect

H

A = B

logic diagram (positive logic)

1OE

1B

1A

2OE

2B

2A

3OE

3B

3A

4OE

4B

4A

Pin numbers shown are for the D, DGV, and PW packages.

2

1

5

4

9

10

12

13

3

6

8

11

1

2

3

4

5

6

7

14

13

12

11

10

9

8

1OE

1A

1B

2OE

2A

2B

GND

4OE

4A

4B

3OE

3A

3B

D, DGV, OR PW PACKAGE

(TOP VIEW)

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

NC

1OE

1A

1B

2OE

2A

2B

GND

4OE

4A

4B

3OE

3A

3B

NC

DBQ PACKAGE

(TOP VIEW)

NC – No internal connection

Copyright

© 1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.