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SN74TVC16222DLR Arkusz danych(PDF) 4 Page - Texas Instruments |
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SN74TVC16222DLR Arkusz danych(HTML) 4 Page - Texas Instruments |
4 / 15 page SN74TVC16222A 22BIT VOLTAGE CLAMP SCDS087G − APRIL 1999 − REVISED APRIL 2005 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PARAMETER MEASUREMENT INFORMATION tPLHREF tPHLREF 2.5 V 0 V 2.5 V VOL Input Tester VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Reference TESTER CALIBRATION SETUP (see Note C) VOL Output Device Under Test tPLHDUT tPLH (see Note D) tPHLDUT tPHL (see Note E) 2.5 V 200 k Ω 3.3 V RDPU = 150 Ω Open-Drain Test Interface Motherboard Interface 2 A1 (VREF) 1 GATE 48 B1 (VBIAS) 47 VDPU TVC16222A NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. B. The outputs are measured one at a time, with one transition per measurement. C. Test procedure: tPLHREF and tPHLREF are obtained by measuring the propagation delay of a reference measuring point. tPLHDUT and tPHLDUT are obtained by measuring the propagation delay of the device under test. D. tPLH = tPLHDUT − tPLHREF E. tPHL = tPHLDUT − tPHLREF B2 46 RDPU = 150 Ω RDPU = 150 Ω RDPU = 150 Ω B3 45 B4 44 B23 25 3 A2 (VS) 4 A3 (VS) 5 A4 (VS) 24 A23 (VS) 1.25 V 1.25 V 1.25 V 1.25 V 1.25 V 1.25 V †† † † §§ § § ‡ Output tested Output reference Input tested † ‡ § DEFINITION SYMBOL GATE Figure 1. Tester Calibration Setup and Voltage Waveforms |
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