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TL16C550A Arkusz danych(PDF) 3 Page - Texas Instruments |
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TL16C550A Arkusz danych(HTML) 3 Page - Texas Instruments |
3 / 31 page TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT SLLS057D – AUGUST 1989 – REVISED MARCH 1996 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 block diagram Receiver Buffer Register Divisor Latch (LS) Divisor Latch (MS) Baud Generator Receiver FIFO Line Status Register Transmitter Holding Register Modem Control Register Modem Status Register Receiver Buffer Register Line Control Register Receiver Timing and Control Line Control Register Transmitter FIFO S e l e c t Line Control Register Modem Control Logic Interrupt Enable Register Interrupt I/O Register FIFO Control Register Select and Control Logic Power Supply Interrupt Control Logic S e l e c t Line Control Register BAUDOUT SIN RCLK SOUT RTS CTS DTR DSR DCD RI OUT1 OUT2 INTRPT 32 36 33 37 38 39 34 31 30 11 9 10 15 CS0 CS1 CS2 ADS MR RD1 RD2 WR1 12 13 14 25 35 21 22 18 WR2 DDIS TXRDY XIN XOUT RXRDY 19 23 24 16 17 29 A0 A1 A2 28 27 26 D7 – D0 8–1 Internal Data Bus VCC VSS 40 20 NOTE A: Terminal numbers shown are for the N package. |
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