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TL16C752 Arkusz danych(PDF) 9 Page - Texas Instruments

Numer części TL16C752
Szczegółowy opis  3.3-V DUAL UART WITH 64-BYTE FIFO
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TL16C752
3.3-V DUAL UART WITH 64-BYTE FIFO
SLLS305 – MAY 1999
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
functional description (continued)
reset
Table 2 summarizes the state of registers after reset.
Table 2. Register Reset Functions
REGISTER
RESET
CONTROL
RESET STATE
Interrupt enable register
RESET
All bits cleared
Interrupt identification register
RESET
Bit 0 is set. All other bits cleared.
FIFO control register
RESET
All bits cleared
Line control register
RESET
Reset to 00011101 (1D hex).
Modem control register
RESET
All bits cleared
Line status register
RESET
Bits 5 and 6 set. All other bits cleared.
Modem status register
RESET
Bits 0–3 cleared. Bits 4–7 input signals.
Enhanced feature register
RESET
All bits cleared
Receiver holding register
RESET
Pointer logic cleared
Transmitter holding register
RESET
Pointer logic cleared
Transmission control register
RESET
All bits cleared
Trigger level register
RESET
All bits cleared
NOTE: Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal
RESEST, i.e., they hold their initialization values during reset.
Table 3 summarizes the state of registers after reset.
Table 3. Signal Reset Functions
SIGNAL
RESET
CONTROL
RESET STATE
TX
RESET
High
RTS
RESET
High
DTR
RESET
High
RXRDY
RESET
High
TXRDY
RESET
Low
interrupts
The TL16C752 has interrupt generation and prioritization (6 prioritized levels of interrupts) capability. The
Interrupt enable register (IER) enables each of the 6 types of interrupts and the INT signal in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0–3, 5–7. When an interrupt
is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5–0].
Table 4 summarizes the interrupt control functions.


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