TL7702B, TL7705B

SUPPLY-VOLTAGE SUPERVISORS

SLVS037H – SEPTEMBER 1989 – REVISED JULY 1999

9

POST OFFICE BOX 655303

Figure 4

14

10

8

6

02

4

6

8

10

18

20

ASSERTION TIME

vs

LOAD RESISTANCE

16

12

RL – Load Resistance – kΩ

VCC = 5 V

CT = 0.1 µF

CL = 10 pF

TA = 25°C

RESET tr

RESET tf

Figure 5

400

200

100

0

02

4

6

8

10

600

700

DEASSERTION TIME

vs

LOAD RESISTANCE

500

300

RL – Load Resistance – kΩ

VCC = 5 V

CT = 0.1 µF

CL = 10 pF

TA = 25°C

RESET tf

RESET tr

RESET tr

RESET tf

Figure 6

24

18

12

6

0

25

50

75

100

125

30

36

ASSERTION TIME

vs

LOAD CAPACITANCE

150

175

200

VCC = 5 V

CT = 0.1 µF

RL = 4.7 kΩ

TA = 25°C

RESET tr

RESET tf

CL – Load Capacitance – pF

Figure 7

0.9

0.7

0.5

0.3

0

25

50

75

100

125

1.1

1.3

DEASSERTION TIME

vs

LOAD CAPACITANCE

150

175

200

1.7

1.5

1.9

2.1

VCC = 5 V

CT = 0.1 µF

RL = 4.7 kΩ

TA = 25°C

RESET tf and RESET tr

CL – Load Capacitance – pF

† For proper operation, both RESET and RESET should be terminated with resistors of similar value. Failure to do so may cause unwanted

plateauing in either output waveform during switching.