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TLC1541FN Arkusz danych(PDF) 9 Page - Texas Instruments |
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TLC1541FN Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 11 page TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION The TLC1541 is a complete data acquisition system on a single chip. The device includes such functions as sample and hold, 10-bit A/D converter, data and control registers, and control logic. For flexibility and access speed, there are four control inputs: chip select (CS), address input, I/O clock, and system clock. These control inputs and a TTL-compatible, 3-state output are intended for serial communications with a microprocessor or microcomputer. The TLC1541 can complete conversions in a maximum of 21 µs, while complete input-conversion output cycles can be repeated at a maximum of 31 µs. The system and I/O clocks are normally used independently and do not require any special speed or phase relationships between them. This independence simplifies the hardware and software control tasks for the device. Once a clock signal within the specification range is applied to the SYSTEM CLOCK input, the control hardware and software need only be concerned with addressing the desired analog channel, reading the previous conversion result, and starting the conversion by using I/O CLOCK. SYSTEM CLOCK drives the conversion-crunching circuitry so that the control hardware and software need not be concerned with this task. When CS is high, DATA OUT is in a 3-state condition and ADDRESS INPUT and I/O CLOCK are disabled. This feature allows each of these terminals, with the exception of the CS terminal, to share a control logic point with its counterpart terminals on additional A/D devices when using additional TLC1541 devices. In this way, the above feature serves to minimize the required control logic terminals when using multiple A/D devices. The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain the conversion result. A normal control sequence is: 1. CS is brought low. To minimize errors caused by noise at the CS input, the internal circuitry waits for two rising edges and then a falling edge of SYSTEM CLOCK after a low CS transition before recognizing the low transition. This technique protects the device against noise when the device is used in a noisy environment. The MSB of the previous conversion result automatically appears on DATA OUT. 2. A new positive-logic multiplexer address shifts in on the first four rising edges of I/O CLOCK. The MSB of the address shifts in first. The negative edges of these four I/O clock pulses shift out the second, third, fourth, and fifth most-significant bits of the previous conversion result. The on-chip sample-and-hold begins sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically involves the charging of internal capacitors to the level of the analog input voltage. 3. Five clock cycles are then applied to the I/O CLOCK, and the sixth, seventh, eighth, ninth, and tenth conversion bits shift out on the negative edges of these clock cycles. 4. The final tenth-clock cycle is applied to the I/O CLOCK. The falling edge of this clock cycle completes the analog sampling process and initiates the hold function. Conversion is then performed during the next 44 system clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low for at least 44 system-clock cycles to allow for the conversion function. CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple conversion, special care must be exercised to prevent noise glitches on I/O CLOCK. When glitches occur on I/O CLOCK, the I/O sequence between the microprocessor/controller and the device loses synchronization. Also, when CS goes high, it must remain high until the end of the conversion. Otherwise, a valid falling edge of CS causes a reset condition, which aborts the conversion in progress. A new conversion may be started and the ongoing conversion simultaneously aborted by performing steps 1 through 4 before the 44 system-clock cycles occur. Such action yields the conversion result of the previous conversion and not the ongoing conversion. |
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