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TPIC46L02DB Arkusz danych(PDF) 2 Page - Texas Instruments

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Numer części TPIC46L02DB
Szczegółowy opis  6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
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TPIC46L02DB Arkusz danych(HTML) 2 Page - Texas Instruments

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TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
For serial operation, the control device must transition CS from high to low to activate the serial input interface.
When this occurs, SDO is enabled, fault data is latched into the serial input interface, and the FLT flag is
refreshed.
Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must
consist of 8 bits of data. In applications where multiple devices are cascaded together, the string of data must
consist of 8 bits for each device. A high data bit turns the respective output channel on and a low data bit turns
it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data
consists of fault flags for the over-battery voltage (bit 8), under-battery voltage (bit 7) (not on TPIC46L03) and
shorted/open-load flags (bits 1-6) for each of the six output channels. A logic-high bit in the fault data indicates
a fault and a logic-low bit indicates that no fault is present on that channel. Fault register bits are set or cleared
asynchronously to reflect the current state of the hardware. The fault must be present when CS is transitioned
from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial
register when CS is low. CS must be transitioned high after all of the serial data has been clocked into the device.
A low-to-high transition of CS transfers the last six bits of serial data to the output buffer, puts SDO in a
high-impedance state, and clears and re-enables the fault register. The TPIC46L01/L02/L03 was designed to
allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the
controller. Serial input data flows through the device and is transferred out SDO following the fault data in
cascaded configurations.
For parallel operation, data is asynchronously transferred directly from the parallel input interface (IN0-IN5) to
the respective GATE output. SCLK or CS are not required for parallel control. A 1 on the parallel input turns the
respective channel on, where a 0 turns it off. Note that either the serial interface or the parallel interface can
enable a channel. Under parallel operation, fault data must still be collected through the serial data interface.
The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions
in the on and off states respectively. These devices offer the option of using an internally generated
fault-reference voltage or an externally supplied VCOMP for fault detection. The internal fault reference is
selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN
to VCC. The drain voltage is compared to the fault-reference voltage when the channel is turned on to detect
shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted-load fault
occurs using the TPIC46L01 or TPIC46L03, the channel is turned off and a fault signal is sent to FLT as well
as to the serial fault-register bit. When a shorted-load fault occurs while using the TPIC46L02, the channel
transitions into a low-duty-cycle, pulse-width-modulated (PWM) signal as long as the fault is present.
Shorted-load conditions must be present for at least the shorted-load deglitch time, t(STBDG), in order to be
flagged as a fault. A fault signal is sent to FLT as well as the serial fault register bit. More detail on fault detection
operation is presented in the device operation section of this data sheet.
The TPIC46L01 and TPIC46L02 provide protection from over-battery voltage and under-battery voltage
conditions irrespective of the state of the output channels. The TPIC46L03 provides protection from over-battery
voltage conditions irrespective of the state of the output channels When the battery voltage is greater than the
overvoltage threshold or less than the undervoltage threshold (except for the TPIC46L03, which has no
undervoltage threshold), all channels are disabled and a fault signal is sent to FLT as well as to the respective
fault register bits. The outputs return to normal operation once the battery voltage fault has been corrected.
When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables
fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are
re-enabled after the battery fault condition has been corrected.
These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect
the FET. This clamp voltage is defined by the sum of VC and turn-on voltage of the external FET. The predriver
also provides a gate-to-source voltage (VGS) clamp to protect the GATE-source terminals of the power FET from
exceeding their rated voltages.
These devices provide pulldown resistors on all inputs except CS. A pullup resistor is used on CS.


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