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TSB41LV03A Arkusz danych(PDF) 4 Page - Texas Instruments

Numer części TSB41LV03A
Szczegółowy opis  IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER
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Strona internetowa  http://www.ti.com
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TSB41LV03A Arkusz danych(HTML) 4 Page - Texas Instruments

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TSB41LV03A, TSB41LV03AI
IEEE 1394a THREE-PORT CABLE TRANSCEIVER/ARBITER
SLLS364A – JULY 1999 – REVISED MAY 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description (continued)
The LPS input is considered inactive if it remains low for more than 2.6
µs and is considered active otherwise.
When the TSB41LV03A detects that LPS is inactive, it will place the PHY-LLC interface into a low–power reset
state in which the CTL and D outputs are held in the logic zero state and the LREQ input is ignored; however,
the SYSCLK output remains active. If the LPS input remains low for more than 26
µs, the PHY-LLC interface
is put into a low–power disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface
is also held in the disabled state during hardware reset. The TSB41LV03A will continue the necessary repeater
functions required for normal network operation regardless of the state of the PHY–LLC interface. When the
interface is in the reset or disabled state and LPS is again observed active, the PHY will initialize the interface
and return it to normal operation.
When the PHY-LLC interface in the low-power disabled state, the TSB41LV03A will automatically enter a
low-power mode if all ports are inactive (disconnected, disabled, or suspended). In this low-power mode, the
TSB41LV03A disables its internal clock generators and also disables various voltage and current reference
circuits depending on the state of the ports (some reference circuitry must remain active in order to detect new
cable connections, disconnections, or incoming TPBias, for example). The lowest power consumption (the
ultra
low-power sleep mode) is attained when all ports are either disconnected, or disabled with the port’s interrupt
enable bit cleared. The TSB41LV03A will exit the low-power mode when the LPS input is asserted high or when
a port event occurs which requires that the TSB41LV03A become active in order to respond to the event or to
notify the LLC of the event (e.g., incoming bias is detected on a suspended port, a disconnection is detected
on a suspended port, a new connection is detected on a nondisabled port, etc.). The SYSCLK output will
become active (and the PHY-LLC interface will be initialized and become operative) within 7.3 ms after LPS is
asserted high when the TSB41LV03A is in the low-power mode.
The PHY uses the C/LKON terminal to notify the LLC to power up and become active. When activated, the
C/LKON signal is a square wave of approximately 163 ns period. The PHY activates the C/LKON output when
the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is
inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet
addressed to this node is received, or conditionally when a PHY interrupt occurs. The PHY deasserts the
C/LKON output when the LLC becomes active (both LPS active and the LCtrl bit set to 1). The PHY also
deasserts the C/LKON output when a bus-reset occurs unless a PHY interrupt condition exists which would
otherwise cause C/LKON to be active.


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