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TSB41LV04APFP Arkusz danych(PDF) 7 Page - Texas Instruments

Numer części TSB41LV04APFP
Szczegółowy opis  IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER
Download  49 Pages
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Producent  TI [Texas Instruments]
Strona internetowa  http://www.ti.com
Logo TI - Texas Instruments

TSB41LV04APFP Arkusz danych(HTML) 7 Page - Texas Instruments

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TSB41LV04A
IEEE 1394a FOUR-PORT CABLE TRANSCEIVER/ARBITER
SLLS379 – OCTOBER 1999
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
TYPE
I/O
DESCRIPTION
NAME
NO.
TYPE
I/O
DESCRIPTION
C/LKON
22
CMOS
I/O
Bus manager contender programming input and link-on output. On hardware reset, this
terminal is used to set the default value of the contender status indicated during self-ID.
Programming is done by tying the terminal through a 10-k
Ω resistor to a high (contender) or
low (not contender). The resistor allows the link-on output to override the input. However, it is
recommended that this terminal should be programmed low, and that the contender status
be set via the C register bit.
If the TSB41LV04A is used with an LLC that has a dedicated terminal for monitoring LKON
and also setting the contender status, then a 10-k
Ω series resistor should be placed on the
LKON line between the PHY and LLC to prevent bus contention.
Following hardware reset, this terminal is the link-on output, which is used to notify the LLC to
power-up and become active. The link-on output is a square-wave signal with a period of
approximately 163 ns (8 SYSCLK cycles) when active. The link-on output is otherwise
driven low, except during Hardware Reset when it is high impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit cleared) and
when:
a) the PHY receives a link-on PHY packet addressed to this node,
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-timeout interrupt), CPSI (cable-power-status interrupt),
or STOI (state-timeout interrupt) register bits are 1 and the RPIE (resuming-port interrupt
enable) register bit is also 1.
Once activated, the link-on output will continue active until the LLC becomes active (both
LPS active and the LCtrl bit set). The PHY also deasserts the link-on output when a bus-reset
occurs unless the link-on output would otherwise be active because one of the interrupt bits
is set (i.e., the link-on output is active due solely to the reception of a link-on PHY packet).
NOTE: If an interrupt condition exists, which would otherwise cause the link-on output to be
activated if the LLC were inactive, the link-on output will be activated when the LLC
subsequently becomes inactive.
CNA
17
CMOS
O
Cable not active output. This terminal is asserted high when there are no ports receiving
incoming bias voltage.
CPS
27
CMOS
I
Cable power status input. This terminal is normally connected to cable power through a
400-k
Ω resistor. This circuit drives an internal comparator that is used to detect the presence
of cable power.
CTL0
CTL1
4
5
CMOS
5 V tol
I/O
Control I/Os. These bidirectional signals control communication between the TSB41LV04A
and the LLC. Bus holders are built into these terminals.
D0 – D7
7, 8, 10, 11, 12,
13, 14, 15
CMOS
5 V tol
I/O
Data I/Os. These are bidirectional data signals between the TSB41LV04A and the LLC. Bus
holders are built into these terminals.
DGND
3, 16, 20, 21,
28, 80
Supply
Digital circuit ground terminals. These terminals should be tied together to the low
impedance circuit board ground plane.
DVDD
6, 29, 30, 79
Supply
Digital circuit power terminals. A combination of high frequency decoupling capacitors near
each terminal are suggested, such as paralleled 0.1
µF and 0.001 µF. Lower frequency
10-
µF filtering capacitors are also recommended. These supply terminals are separated
from PLLVDD and AVDD internal to the device to provide noise isolation. They should be tied
at a low impedance point on the circuit board.
FILTER0
FILTER1
71
72
CMOS
I/O
PLL filter terminals. These terminals are connected to an external capacitance to form a
lag-lead filter required for stable operation of the internal frequency multiplier PLL running off
of the crystal oscillator. A 0.1-
µF ±10% capacitor is the only external component required to
complete this filter.
ISO
26
CMOS
I
Link interface isolation control input. This terminal controls the operation of output
differentiation logic on the CTL and D terminals. If an optional Annex J type isolation barrier is
implemented between the TSB41LV04A and LLC, the ISO terminal should be tied low to
enable the differentiation logic. If no isolation barrier is implemented (direct connection), or TI
bus holder isolation is implemented, the ISO terminal should be tied high to disable the
differentiation logic. For additional information refer to TI application note
Serial Bus
Galvanic Isolation, SLLA011.


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