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ADT7310TRZ Arkusz danych(PDF) 4 Page - Analog Devices

Numer części ADT7310TRZ
Szczegółowy opis  짹0.5째C Accurate, 16-Bit Digital SPI Temperature Sensor
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Strona internetowa  http://www.analog.com
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ADT7310
Rev. 0 | Page 4 of 24
SPI TIMING SPECIFICATIONS
TA = −55°C to +150°C, VDD = 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (tR) = fall time (tF) = 5 ns
(10% to 90% of VDD) and timed from a voltage level of 1.6 V.
Table 2.
Parameter1, 2
Limit at TMIN, TMAX (B Version)
Unit
Conditions/Comments
t1
0
ns min
CS falling edge to SCLK active edge setup time3
t2
100
ns min
SCLK high pulse width
t3
100
ns min
SCLK low pulse width
t4
30
ns min
Data valid to SCLK edge setup time
t5
25
ns min
Data valid to SCLK edge hold time
t6
0
ns min
SCLK active edge to data valid delay3
60
ns max
VDD = 4.5 V to 5.5 V
80
ns max
VDD = 2.7 V to 3.6 V
t74
10
ns min
Bus relinquish time after CS inactive edge
80
ns max
t8
0
ns min
CS rising edge to SCLK edge hold time
t9
0
ns min
CS falling edge to DOUT active time
60
ns max
VDD = 4.5 V to 5.5 V
80
ns max
VDD = 2.7 V to 3.6 V
t10
10
ns min
SCLK inactive edge to DOUT high
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2 See Figure 2.
3 SCLK active edge is falling edge of SCLK.
4 This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading
capacitances.
CS
SCLK
DIN
DOUT
t1
1
8
7
MSB
LSB
23
MSB
LSB
12
7
8
t2
t4
t5
t3
t6
t7
t8
t9
t10
Figure 2. Detailed SPI Timing Diagram
1.6V
10pF
TO
OUTPUT
PIN
ISINK (1.6mA WITH VDD = 5V,
100µA WITH VDD = 3V)
ISOURCE (200µA WITH VDD =5V,
100µA WITH VDD = 3V)
Figure 3. Load Circuit for Timing Characterization


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