ADuM4160

Rev. A | Page 8 of 16

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PDEN

4

16

15

14

SPD

13

SPU

5

PIN

12

UD–

6

DD–

11

UD+

7

DD+

10

9

ADuM4160

TOP VIEW

(Not to Scale)

NC = NO CONNECT

*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED, AND CONNECTING

Figure 3. Pin Configuration

Table 9. Pin Function Descriptions

Pin No.

Mnemonic Direction Description

1

Power

Input Power Supply for Side 1. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V,

2

Return

Ground 1. Ground reference for Isolator Side 1.

3

Power

4

PDEN

Input

disconnected, allowing buffer impedance measurements.

5

SPU

Input

Speed Select Upstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic

conventions when SPU is high, and low speed slew rate, timing, and logic conventions when SPU is tied

match Pin 13.

6

UD−

I/O

Upstream D−.

7

UD+

I/O

Upstream D+.

8

Return

Ground 1. Ground reference for Isolator Side 1.

9

Return

Ground 2. Ground reference for Isolator Side 2.

10

DD+

I/O

Downstream D+.

11

DD−

I/O

Downstream D−.

12

PIN

Input

Upstream Pull-Up Enable. PIN controls the power connection to the pull-up for the upstream port. It can

delayed enumeration.

13

SPD

Input

Speed Select Downstream Buffer. Active high logic input. Selects full speed slew rate, timing, and logic

conventions when SPD is high, and low speed slew rate, timing, and logic conventions when SPD is tied

Pin 5.

14

Power

15

Return

Ground 2. Ground reference for Isolator Side 2.

16

Power

Input Power Supply for Side 2. Where the isolator is powered by the USB bus voltage, 4.5 V to 5.5 V,