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FAN6210MY Arkusz danych(PDF) 8 Page - Fairchild Semiconductor |
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FAN6210MY Arkusz danych(HTML) 8 Page - Fairchild Semiconductor |
8 / 11 page © 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN6210 Rev. 1.0.1 8 SIN SOUT DET 300ns 100ns 700ns Programmable delay 700ns XP XN 50ns 50ns 300ns 50ns 300ns 300ns 50ns 300ns Programmable delay Gate drive for Powering SR Gate drive for Free-wheeling SR SIN SOUT DET 300ns 100ns 700ns Programmable delay 700ns XP XN 50ns 50ns 300ns 50ns 300ns 300ns 50ns 300ns Programmable delay Gate drive for Powering SR Gate drive for Free-wheeling SR Heavy load condition Light load condition Figure 16. Timing Diagram t DLY_XP (ns) R RDLY (kΩ) 100 150 200 250 300 350 57.5 10 12.5 15 17.5 20 22.5 25 Figure 17. Programmable Delay with Resistor Under-Voltage Lockout (UVLO) The power-on and -off threshold of FAN6210 are fixed at 10V and 8V, respectively. The VDD pin can be connected with the power source of the PWM controller. VDD Pin Over-Voltage Protection VDD over-voltage protection prevents damage due to abnormal conditions. Once the VDD voltage exceeds the VDD over-voltage protection voltage (VDD-OVP) and lasts for tOVP, FAN6210 stops operation. Green-Mode Operation To improve light-load efficiency, green-mode operation is employed, which disables the SR turn-on trigger signal, minimizing gate drive power consumption at light-load condition. Green mode is enabled when the duty cycle of SIN is smaller than 10%. |
Podobny numer części - FAN6210MY |
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Podobny opis - FAN6210MY |
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