Preliminary Data Sheet E0187N10

4

Block Diagram

DM0

SDRAMs (D0 to D7)

SDRAMs (D0 to D7)

BA0 to BA1

SDRAMs (D0 to D7)

CKE0

SDRAMs (D0 to D3)

CKE1

SDRAMs (D4 to D7)

VDDSPD

SPD

VREF

SDRAMs (D0 to D7)

VDD

SDRAMs (D0 to D7),

and

VSS

VDDID

VDD

VDDQ

Open

SDRAMs (D0 to D7), SPD

Serial PD

SDA

A0

A1

A2

WP

SCL

SA0

SA1

SA2

SDA

SCL

Notes :

1. DQ wiring may differ from that described

in this drawing; however DQ/DM/DQS

relationships are maintained as shown.

VDDID strap connections:

(for memory device VDD, VDDQ)

Strap out (open): VDD = VDDQ

Strap in (closed): VDD ≠ VDDQ

DQS0

DQ0 to DQ7

8

D0

/RAS

/CAS

/WE

A0 to AN

SDRAMs (D0 to D7)

SDRAMs (D0 to D7)

4 loads

CK0

/CK0

4 loads

CK1

/CK1

0 loads

CK2

/CK2

/S0

/S1

/S

D2

/S

LDQS

LDM

I/O0 to I/O7

RS

RS

RS

DM1

DQS1

DQ8 to DQ15

8

UDQS

UDM

I/O8 to I/O15

RS

RS

RS

DM4

DQS4

DQ32 to DQ39

8

RS

RS

RS

DM5

DQS5

DQ40 to DQ47

8

RS

RS

RS

LDQS

LDM

I/O0 to I/O7

UDQS

UDM

I/O8 to I/O15

DM2

DQS2

DQ16 to DQ23

8

D1

/S

D3

/S

LDQS

LDM

I/O0 to I/O7

RS

RS

RS

DM3

DQS3

DQ24 to DQ31

8

UDQS

UDM

I/O8 to I/O15

D4

/S

LDQS

LDM

I/O0 to I/O7

UDQS

UDM

I/O8 to I/O15

D5

/S

LDQS

LDM

I/O0 to I/O7

UDQS

UDM

I/O8 to I/O15

RS

RS

RS

DM6

DQS6

DQ48 to DQ55

8

RS

RS

RS

DM7

DQS7

DQ56 to DQ63

8

RS

RS

RS

LDQS

LDM

I/O0 to I/O7

UDQS

UDM

I/O8 to I/O15

D6

/S

LDQS

LDM

I/O0 to I/O7

UDQS

UDM

I/O8 to I/O15

D7

/S

LDQS

LDM

I/O0 to I/O7

UDQS

UDM

I/O8 to I/O15

Remarks 1. The value of all resistors of DQs, DQSs, DM/DQSs is 22

Ω.± 5%

2. D0 – D7:

µPD45D128164 (2M words × 16 bits × 4 banks)