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ADAU1381BCPZ-RL7 Arkusz danych(PDF) 6 Page - Analog Devices |
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ADAU1381BCPZ-RL7 Arkusz danych(HTML) 6 Page - Analog Devices |
6 / 84 page ADAU1381 Rev. 0 | Page 6 of 84 Parameter Test Conditions/Comments Min Typ Max Unit Dynamic Range −60 dB input With A-Weighted Filter (RMS) AVDD = 1.8 V 99 dB AVDD = 3.3 V 105 dB No Filter (RMS) AVDD = 1.8 V 96 dB AVDD = 3.3 V 102 dB Beep Input Mute Attenuation AVDD = 3.3 V; mute set by Register 0x4008, Bit 3 −90 dB Offset Error AVDD = 3.3 V 10 mV Gain Error AVDD = 3.3 V −0.3 dB Interchannel Gain Mismatch 30 mdB Beep Input PGA Gain Range AVDD = 3.3 V −23 +32 dB Beep Playback Mixer Gain Range AVDD = 3.3 V −15 +6 dB Power Supply Rejection Ratio CM capacitor = 10 μF AVDD = 3.3 V, 100 mV p-p at 217 Hz −58 dB AVDD = 3.3 V, 100 mV p-p at 1 kHz −72 dB MICROPHONE BIAS Microphone bias enabled Bias Voltage 0.65 × AVDD AVDD = 1.8 V, low bias 1.17 V AVDD = 3.3 V, low bias 2.145 V 0.90 × AVDD AVDD = 1.8 V, high bias 1.62 V AVDD = 3.3 V, high bias 2.97 V Bias Current Source AVDD = 3.3 V, high bias, high performance 5 mA Noise in the Signal Bandwidth AVDD = 3.3 V, 20 Hz to 20 kHz High bias, high performance 39 nV√Hz High bias, low performance 78 nV√Hz Low bias, high performance 25 nV√Hz Low bias, low performance 35 nV√Hz AVDD = 1.8 V, 20 Hz to 20 kHz High bias, high performance 35 nV√Hz High bias, low performance 45 nV√Hz Low bias, high performance 23 nV√Hz Low bias, low performance 23 nV√Hz OUTPUT SIDE PERFORMANCE SPECIFICATIONS Specifications guaranteed at 25°C (ambient). Table 2. Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL-TO-ANALOG CONVERTERS DAC Resolution All DACs 24 Bits Digital Attenuation Step 0.375 dB Digital Attenuation Range 95 dB DAC TO LINE OUTPUT PATH Full-Scale Output Voltage (0 dB) Scales linearly with AVDD AVDD/3.3 V rms AVDD = 1.8 V 0.55 (1.56) V rms (V p-p) AVDD = 3.3 V 1.0 (2.83) V rms (V p-p) Line Output Mute Attenuation, DAC to Mixer Path Muted AVDD = 3.3 V; mute set by Register 0x401C, Bit 5, and Register 0x401E, Bit 6 −85 dB Line Output Mute Attenuation, Line Output Muted AVDD = 3.3 V; mute set by Register 0x4025, Bit 1, and Register 0x4026, Bit 1 −85 dB |
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