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AM3505 Arkusz danych(PDF) 4 Page - Texas Instruments |
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AM3505 Arkusz danych(HTML) 4 Page - Texas Instruments |
4 / 184 page 1.3 Functional Block Diagram 64 64 Async 64 64 L2$ 256K MPU Subsystem ARM Cortex- A8 TM Core 16K/16K L1$ POWERVR SGX Graphics Accelerator ( only) TM AM3517 32 32 32 Channel System DMA 32 32 Analog DAC LCD Panel CVBS or S-Video Dual Output 3-Layer Display Processor (1xGraphics, 2xVideo) Temporal Dithering SDTV → QCIF Support 32 HS/FS/ LS USB Host 32 L3 Interconnect Network-Hierarchial, Performance, and Power Driven 64K On-Chip RAM 32 132K On-Chip BOOT ROM SMS: SDRAM Memory Scheduler/ Rotation 64 SDRC Controller L4 Interconnect 32 System Controls PRCM External Peripherals Interfaces Peripherals: 4xUART, 3xHigh-Speed I2C, 5xMcBSP (2x with Sidetone/Audio Buffer) 4xMcSPI, 186xGPIO, 3xHigh-Speed MMC/SDIO, HDQ/1 Wire, 12xGPTimers, 1xWDT, 32K Sync Timer GPMC: General Purpose Memory Controller 32 Emulation Debug: SDTI, ETM, JTAG, Coresight TM DAP External DDR2 32 SPRS550-006 Parallel HECC EMAC VPFE USB PHY USB OTG Controller DDR PHY NAND/NOR/ FLASH, SRAM USB transceivers / device ports [3] AM3517/05 ARM Microprocessor SPRS550 – OCTOBER 2009 www.ti.com Figure 1-1 shows the functional block diagram of the AM3517/05 ARM Microprocessor. Figure 1-1. AM3517/05 Functional Block Diagram 4 AM3517/05 ARM Microprocessor Submit Documentation Feedback |
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