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TSC80C51-25MF Arkusz danych(PDF) 6 Page - TEMIC Semiconductors |
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TSC80C51-25MF Arkusz danych(HTML) 6 Page - TEMIC Semiconductors |
6 / 19 page TSC80C31/80C51 Rev. E (14 Jan.97) 6 MATRA MHS The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits. When Idle mode is terminated by an enabled interrupt, the service routine can examine the status of the flag bits. The second way of terminating the Idle mode is with a hardware reset. Since the oscillator is still running, the hardware reset needs to be active for only 2 machine cycles (24 oscillator periods) to complete the reset operation. Power Down Mode The instruction that sets PCON.1 is the last executed prior to entering power down. Once in power down, the oscillator is stopped. The contents of the onchip RAM and the Special Function Register is saved during power down mode. The hardware reset initiates the Special Fucntion Register. In the Power Down mode, VCC may be lowered to mi-nimize circuit power consumption. Care must be taken to ensure the voltage is not reduced until the power down mode is entered, and that the voltage is restored before the hardware reset is applied which freezes the oscillator. Reset should not be released until the oscillator has restarted and stabilized. A hardware reset is the only way of exiting the power down mode. Table 1 describes the status of the external pins while in the power down mode. It should be noted that if the power down mode is activated while in external program memory, the port data that is held in the Special Function Register P2 is restored to Port 2. If the data is a 1, the port pin is held high during the power down mode by the strong pullup, T1, shown in Figure 4. Table 1. Status of the external pins during idle and power down modes. MODE PROGRAM MEMORY ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal 1 1 Port Data Port Data Port Data Port Data Idle External 1 1 Floating Port Data Address Port Data Power Down Internal 0 0 Port Data Port Data Port Data Port Data Power Down External 0 0 Floating Port Data Port Data Port Data Stop Clock Mode Due to static design, the TSC80C31/80C51 clock speed can be reduced until 0 MHz without any data loss in memory or registers. This mode allows step by step utilization, and permits to reduce system power consumption by bringing the clock frequency down to any value. At 0 MHz, the power consumption is the same as in the Power Down Mode. I/O Ports The I/O buffers for Ports 1, 2 and 3 are implemented as shown in Figure 4. Figure 4. I/O Buffers in the TSC80C31/80C51 (Ports 1, 2, 3). |
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