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ATmega16-16PU Arkusz danych(PDF) 68 Page - ATMEL Corporation

Numer części ATmega16-16PU
Szczegółowy opis  8-bit Microcontroller with 16K Bytes In-Syustem Programmable Flash
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ATmega16-16PU Arkusz danych(HTML) 68 Page - ATMEL Corporation

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68
2466S–AVR–05/09
ATmega16(L)
External
Interrupts
The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled,
the interrupts will trigger even if the INT0..2 pins are configured as outputs. This feature provides
a way of generating a software interrupt. The external interrupts can be triggered by a falling or
rising edge or a low level (INT2 is only an edge triggered interrupt). This is set up as indicated in
the specification for the MCU Control Register – MCUCR – and MCU Control and Status Regis-
ter – MCUCSR. When the external interrupt is enabled and is configured as level triggered (only
INT0/INT1), the interrupt will trigger as long as the pin is held low. Note that recognition of falling
or rising edge interrupts on INT0 and INT1 requires the presence of an I/O clock, described in
“Clock Systems and their Distribution” on page 24. Low level interrupts on INT0/INT1 and the
edge interrupt on INT2 are detected asynchronously. This implies that these interrupts can be
used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in
all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. This makes the MCU less sensitive to
noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the
Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25
⋅C. The frequency of the Watchdog Oscilla-
tor is voltage dependent as shown in “Electrical Characteristics” on page 291. The MCU will
wake up if the input has the required level during this sampling or if it is held until the end of the
start-up time. The start-up time is defined by the SUT Fuses as described in “System Clock and
Clock Options” on page 24. If the level is sampled twice by the Watchdog Oscillator clock but
disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be
generated. The required level must be held long enough for the MCU to complete the wake up to
trigger the level interrupt.
MCU Control Register
– MCUCR
The MCU Control Register contains control bits for interrupt sense control and general MCU
functions.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and the corre-
sponding interrupt mask in the GICR are set. The level and edges on the external INT1 pin that
activate the interrupt are defined in Table 34. The value on the INT1 pin is sampled before
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If
low level interrupt is selected, the low level must be held until the completion of the currently
executing instruction to generate an interrupt.
Bit
765
4321
0
SM2
SE
SM1
SM0
ISC11
ISC10
ISC01
ISC00
MCUCR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
000
0000
0
Table 34. Interrupt 1 Sense Control
ISC11
ISC10
Description
0
0
The low level of INT1 generates an interrupt request.
0
1
Any logical change on INT1 generates an interrupt request.
1
0
The falling edge of INT1 generates an interrupt request.
1
1
The rising edge of INT1 generates an interrupt request.


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