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ATmega16-16PU Arkusz danych(PDF) 69 Page - ATMEL Corporation

Numer części ATmega16-16PU
Szczegółowy opis  8-bit Microcontroller with 16K Bytes In-Syustem Programmable Flash
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ATmega16-16PU Arkusz danych(HTML) 69 Page - ATMEL Corporation

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2466S–AVR–05/09
ATmega16(L)
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 35. The value on the INT0 pin is sampled before detecting edges.
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
MCU Control and
Status Register –
MCUCSR
• Bit 6 – ISC2: Interrupt Sense Control 2
The Asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG I-bit and
the corresponding interrupt mask in GICR are set. If ISC2 is written to zero, a falling edge on
INT2 activates the interrupt. If ISC2 is written to one, a rising edge on INT2 activates the inter-
rupt. Edges on INT2 are registered asynchronously. Pulses on INT2 wider than the minimum
pulse width given in Table 36 will generate an interrupt. Shorter pulses are not guaranteed to
generate an interrupt. When changing the ISC2 bit, an interrupt can occur. Therefore, it is rec-
ommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR Register. Then,
the ISC2 bit can be changed. Finally, the INT2 Interrupt Flag should be cleared by writing a logi-
cal one to its Interrupt Flag bit (INTF2) in the GIFR Register before the interrupt is re-enabled.
General Interrupt
Control Register –
GICR
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU
General Control Register (MCUCR) define whether the External Interrupt is activated on rising
Table 35. Interrupt 0 Sense Control
ISC01
ISC00
Description
0
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
1
The rising edge of INT0 generates an interrupt request.
Bit
765
432
10
JTD
ISC2
JTRF
WDRF
BORF
EXTRF
PORF
MCUCSR
Read/Write
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
See Bit Description
Table 36. Asynchronous External Interrupt Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
tINT
Minimum pulse width for
asynchronous external interrupt
50
ns
Bit
7
654
32
10
INT1
INT0
INT2
IVSEL
IVCE
GICR
Read/Write
R/W
R/W
R/W
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0


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