ADAU1781BCPZ datasheet(8/88 Pages) AD

Numer części	ADAU1781BCPZ

Szczegółowy opis	Low Noise Stereo Codec with SigmaDSP Processing Core

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ADAU1781

Rev. 0 | Page 8 of 88

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Total Harmonic Distortion + Noise

8 Ω, 1 nF load, AVDD = 1.8 V, PO = 50 mW

−60

dB

AVDD = 3.3 V, PO = 175 mW

−60

dB

Dynamic Range

−60 dB input

With A-Weighted Filter (RMS)

AVDD = 1.8 V

97

dB

AVDD = 3.3 V

103

dB

No Filter (RMS)

AVDD = 1.8 V

94

dB

AVDD = 3.3 V

100

dB

Signal-to-Noise Ratio

With A-Weighted Filter (RMS)

AVDD = 1.8 V

98

dB

AVDD = 3.3 V

103

dB

No Filter (RMS)

AVDD = 1.8 V

96

dB

AVDD = 3.3 V

101

dB

Power Supply Rejection Ratio

CM capacitor = 10 μF

100 mV p-p at 217 Hz

−57

dB

100 mV p-p at 1 kHz

−60

dB

Differential Offset Error

2

mV

Mono Mixer Mute Attenuation,

Beep to Mixer Path Muted

Mute set by Register 0x401F, Bit 0

−90

dB

REFERENCE (CM PIN)

Common-Mode Reference Output

AVDD/2

V

POWER SUPPLY SPECIFICATIONS

AVDD1 and AVDD2 must always be equal. Power supply measurements are taken with the SigmaDSP processing core enabled.

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

AVDD1, AVDD2

1.8

3.3

3.65

V

IOVDD

1.63

3.3

3.65

V

Digital I/O Current (IOVDD = 3.3 V)

20 pF capacitive load on all digital pins

Slave Mode, Analog I/O,

12.288 MHz External MCLK Input

fS = 48 kHz

0.20

mA

fS = 96 kHz

0.35

mA

fS = 8 kHz

0.04

mA

Master Mode, MCKO Disabled

fS = 48 kHz

1.25

mA

fS = 96 kHz

2.50

mA

fS = 8 kHz

0.22

mA

Digital I/O Current (IOVDD = 1.8 V)

20 pF capacitive load on all digital pins

Slave Mode, Analog I/O,

12.288 MHz External MCLK Input

fS = 48 kHz

0.10

mA

fS = 96 kHz

0.18

mA

fS = 8 kHz

0.02

mA

Master Mode, MCKO Disabled

fS = 48 kHz

0.68

mA

fS = 96 kHz

1.33

mA

fS = 8 kHz

0.12

mA

Analog Current (AVDD)

See Table 4

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