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ACE24LC02BN+ Arkusz danych(PDF) 7 Page - ACE Technology Co., LTD. |
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ACE24LC02BN+ Arkusz danych(HTML) 7 Page - ACE Technology Co., LTD. |
7 / 12 page ACE24LC02BN+ Technology Two-wire Serial EEPROM VER 1.3 7 Figure 5.Start and Stop Definition Figure 6.Output Acknowledge Device Addressing The 2K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 7). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins (The A2, A1 and A0 device address bits are “0” for the 2K EEPROM of SOT-23-5 package). The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state. Write Operations Byte Write: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 8). |
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