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DM9000 Arkusz danych(PDF) 7 Page - Davicom Semiconductor, Inc. |
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DM9000 Arkusz danych(HTML) 7 Page - Davicom Semiconductor, Inc. |
7 / 53 page DM9000 ISA to Ethernet MAC Controller with Integrated 10/100 PHY Final 7 Version: DM9000-DS-F03 April 23, 2009 5. Pin Description I= Input, O=Output, I/O= Input/Output, O/D= Open Drain, P= Power, LI= reset Latch Input, #= asserted low 5.1 MII Interface Pin No. Pin Name I/O Description 37 LINK_I I External MII device link status 41,40,39, 38 RXD [3:0] I External MII Receive Data 4-bit nibble data input (synchronous to RXCLK) when in 10/100 Mbps. MII mode 43 CRS I/O External MII Carrier Sense Active high to indicate the pressure of carrier, due to receive or transmit activities in 10 Base-T or 100 Base-TX mode. This pin is output in reverse MII interface. 44 COL I/O External MII Collision Detect. This pin is output in reverse MII interface. 45 RX_DV I External MII Receive Data Valid 46 RX_ER I External MII Receive Error 47 RX_CLK I External MII Receive Clock 49 TX_CLK I/O External MII Transmit Clock. This pin in output in MII interface. 53,52,51, 50 TXD [3:0] O External MII Transmit Data 4-bit nibble data outputs (synchronous to the TX_CLK) when in 10/100Mbps nibble mode TXD [2:0] is also used as the strap pins of IO base address. IO base = (strap pin value of TXD [2:0]) * 10H + 300H 54 TX_ EN O External MII Transmit Enable 56 MDIO I/O MII Serial Management Data 57 MDC O MII Serial Management Data Clock This pin is also used as the strap pin of the polarity of the INT pin When the MDC pin is pulled high, the INT pin is low active; otherwise the INT pin is high active Note: The pins of MII interface are all have a pulled down resistor about 60k ohm internally 5.2 Processor Interface 1 IOR# I Processor Read Command This pin is low active at default, its polarity can be modified by EEPROM setting. See the EEPROM content description for detail 2 IOW# I Processor Write Command This pin is low active at default, its polarity can be modified by EEPROM setting. See the EEPROM content description for detail 3 AEN I Address Enable A low active signal used to select the DM9000. 4 IOWAIT O Processor Command Ready When a command is issued before last command is completed, the IOWAIT will be pulled low to indicate the current command is waited 14 RST I Hardware Reset Command, active high to reset the DM9000 |
Podobny numer części - DM9000_09 |
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Podobny opis - DM9000_09 |
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