ADRF6655-EVALZ datasheet(5/44 Pages) AD

Numer części	ADRF6655-EVALZ

Szczegółowy opis	Broadband Up/Downconverting Mixer with Integrated Fractional-N PLL and VCO

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ADRF6655

Rev. 0 | Page 5 of 44

TIMING CHARACTERISTICS

Table 2. Serial Interface Timing, VCC = 5 V ± 5%

Parameter

Limit

Unit

Test Conditions/Comments

t1

20

ns minimum

LE setup time

t2

10

ns minimum

DATA to CLK setup time

t3

10

ns minimum

DATA to CLK hold time

t4

25

ns minimum

CLK high duration

t5

25

ns minimum

CLK low duration

t6

10

ns minimum

CLK to LE setup time

t7

20

ns minimum

LE pulse width

CLK

DATA

LE

DB23 (MSB)

DB22

DB2

DB1

(CONTROL BIT C2)

(CONTROL BIT C3)

DB0 (LSB)

(CONTROL BIT C1)

t2

t3

t7

t6

t1

t4

t5

Figure 2. Timing Diagram

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