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74ABT827D Arkusz danych(PDF) 7 Page - NXP Semiconductors |
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74ABT827D Arkusz danych(HTML) 7 Page - NXP Semiconductors |
7 / 14 page 74ABT827_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 24 February 2010 7 of 14 NXP Semiconductors 74ABT827 10-bit buffer/line driver; non-inverting; 3-state VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. 3-state enable and disable times 001aal293 tPLZ tPHZ outputs disabled outputs enabled VOH − 0.3 V VOL + 0.3 V outputs enabled output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH OEn input VI VOL VOH 3.5 V VM GND GND tPZL tPZH VM VM a. Input pulse definition b. Test circuit Test data and VEXT levels are given in Table 8. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 7. Test circuit for measuring switching times 001aai298 VM VM tW tW 10 % 90 % 90 % 0 V VI VI negative pulse positive pulse 0 V VM VM 90 % 10 % 90 % 10 % 10 % tf tr tr tf VEXT VCC VI VO mna616 DUT CL RT RL RL G Table 8. Test data Input Load VEXT VI fI tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω open open 7.0 V |
Podobny numer części - 74ABT827D |
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Podobny opis - 74ABT827D |
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