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ADS5400IPZP Arkusz danych(PDF) 9 Page - Texas Instruments |
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ADS5400IPZP Arkusz danych(HTML) 9 Page - Texas Instruments |
9 / 48 page CLKINP RESETP CLKOUT isresetafter 3.5 CLKINcycles (+ tPD-CLKDIV2 ) Phase 0: CLKOUT indesired stateafterpowerup Phase 1: misalignedby 1 clockafterpowerup tPD-CLKDIV2 tRSU tRH DATA BUS A N SYNCOUTA (OVRA pins) Sync SampleNandRESET pulse capturedhere CLKOUTAP IfSYNCmodeisenabled, theOVRA pinsbecomeSYNCOUTA pins LatencyofNandSYNCOUTA arematchedto 7 CLKINcycles t tsu th PD-ADATA N+1 N-1 tCLKL tCLKH N ta N+1 DIFFERENTIAL ANALOGINPUT (INP-INN) Aperture delay N+2 N+2 N output N+1 output ADS5400 www.ti.com SLAS611B – OCT 2009 – REVISED MARCH 2010 Timing Diagrams Propagation delays and setup/hold times not drawn to scale. RESET and SYNCOUT are optional. Any clock phase will work properly, but makes synchronization of data capture across multiple ADCs difficult without a known CLKOUT phase. RESET can be a single pulse (as shown), low-to-high step or repetitive pulse input signal. The frequency of repetitive RESET pulses should not exceed CLKIN/2, and should be an even divisor of CLKIN, in order to keep the CLKOUT phase the same with each RESET event. SYNCOUTA transitions with the same latency as the sample that is present when the RESET pulse is captured, shown here as sample N. Each RESET captured generates a SYNCOUT pulse, which behaves as a data bit. Bus B is not active in single bus mode. Figure 1. Single Bus Mode Copyright © 2009–2010, Texas Instruments Incorporated 9 Product Folder Link(s): ADS5400 |
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