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5V7855-DPK Arkusz danych(PDF) 3 Page - Integrated Device Technology |
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5V7855-DPK Arkusz danych(HTML) 3 Page - Integrated Device Technology |
3 / 14 page IDT5V7855-DPK REVISION A MARCH 11, 2010 3 ©2010 Integrated Device Technology, Inc. IDT5V7855 Data Sheet EEPROM PROGRAMMABLE PLL DIE FOR LVCMOS CRYSTAL OSCILLATOR Functional Description The output frequency of the IDT5V7855 is determined by the crystal frequency and the three programmable divider/multiplier registers: Prescaler (P), Fractional Multiplier (M), and Output Divider (D). The prescaler (P) is a 3-bit integer register while the output divider (D) is a 7-bit integer register. The fractional multiplier (M) is a 19-bit register and has the feature of a fractional component in addition to the integer value. This allows the IDT5V7855 to be programmed to a wide variety of output frequencies from a single input crystal frequency. Figure 1. Simplified Block Diagram The actual values which may be programmed into the various registers depend on the specified operational ranges of some of the PLL components such as the VCO and crystal oscillator. As shown in tables 5 and 6A, these ranges are: VCO Range: 170MHz to 340MHz XTAL Oscillator Range: 16MHz to 50MHz The minimum value permitted for the feedback register is a function of the minimum VCO frequency and the maximum phase detector reference frequency. The maximum phase detector reference frequency is set by the maximum crystal frequency (50MHz) divided by the minimum prescaler divider (1) and is therefore 50MHz. The feedback fractional multiplier register operational range can be determined as: M Min: 170MHz ÷ 50MHz = 3.4 M Max: 31.9993896 ≈ 32 The maximum value that can be programmed into the fractional multiplier (all 19 bits “1”) is approximately 32 (actual value is 31.99993896). Given the VCO range and the feedback divider range, the minimum phase detector frequency can be determined from the minimum VCO frequency and the maximum feedback divider as: Phase Detector Min: 170MHz ÷ 32 = 5.3125MHz Phase Detector Max: 50MHz The maximum value is set by the specified maximum crystal frequency. Prescaler (P) The Prescaler (P) divides down the input crystal frequency prior to the internal phase detector. The prescaler register is a 3-bit register so the possible values which may be programmed are 1 through 7. The specified input crystal frequency range is: 16MHz to 50MHz and the phase detector range is: 5.3125MHz to 50MHz. So the possible settings and ranges are: Table 3A. Prescaler Table Fractional Multiplier (M) The Fractional Multiplier (M) is a 19-bit register. The operational range of the fractional multiplier is 3.4 to approximately 32 (actually 31.99993896). The decimal multiplier value obtained from the 19-bit fractional multiplier register can be determined as: MDEC is the fractional multiplier (decimal) value MBIN is the value programmed in the 19-bit register The fractional portion of the fractional multiplier allows a programming frequency resolution to 61/MDEC ppm. Note that higher MDEC values will produce lower ppm error. Examples: For a fractional multiplier register MBIN of 1010101000000000000 binary The ppm resolution (single LSB bit change in the MBIN) for this setting is: For a fractional multiplier register MBIN of 0010101010000000000 binary The ppm resolution (single LSB bit change in the MBIN) for this setting is: Crystal Range (MHz) Prescaler (P) Phase Detector Frequency (MHz) 16 – 50 1 16 – 50 16 – 50 2 8 – 25 16 – 50 3 5.3333 – 16.6667 21.25 – 50 4 5.3125 – 12.5 26.5625 – 50 5 5.3125 – 10 31.875 – 50 6 5.3125 – 8.3333 37.1875 – 50 7 5.3125 – 7.1429 M DEC M BIN 16384 ---------------- = M DEC 348160 16384 -------------------- 21.2500 == 61ppm 21.25 ------------------- 2.9ppm = M DEC 87040 16384 ---------------- 5.3125 == 61ppm 5.3125 ------------------- 11.5ppm = |
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