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X1205V8 Arkusz danych(PDF) 4 Page - Xicor Inc. |
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X1205V8 Arkusz danych(HTML) 4 Page - Xicor Inc. |
4 / 22 page X1205 – Preliminary Information REV 1.0.9 8/29/02 Characteristics subject to change without notice. 4 of 22 www.xicor.com Table 1. Clock/Control Memory Map Addr. Type Reg Name Bit Range 7 6 543210 003F Status SR BAT AL1 AL0 0 0 RWEL WEL RTCF 01h 0037 RTC (SRAM) Y2K 0 0 Y2K21 Y2K20 Y2K13 0 0 Y2K10 20h 0036 DW 0 0 0 0 0 DY2 DY1 DY0 0-6 00h 0035 YR Y23 Y22 Y21 Y20 Y13 Y12 Y11 Y10 0-99 00h 0034 MO 0 0 0 G20 G13 G12 G11 G10 1-12 00h 0033 DT 0 0 D21 D20 D13 D12 D11 D10 1-31 00h 0032 HR MIL 0 H21 H20 H13 H12 H11 H10 0-23 00h 0031 MN 0 M22 M21 M20 M13 M12 M11 M10 0-59 00h 0030 SC 0 S22 S21 S20 S13 S12 S11 S10 0-59 00h 0013 Control (NONVOLATILE) DTR 0 0 0 0 0 DTR2 DTR1 DTR0 00h 0012 ATR 0 0 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 00h 0011 INT IM AL1E AL0E 0 0 X X X 00h 0010 0 0 0 000000 00h 000F Alarm1 (NONVOLATILE) Y2K1 0 0 A1Y2K21 A1Y2K20 A1Y2K13 0 0 A1Y2K10 20h 000E DWA1 EDW1 0 0 0 0 DY2 DY1 DY0 0-6 00h 000D YRA1 Unused – Default = RTC Year value – Future expansion 000C MOA1 EMO1 0 0 A1G20 A1G13 A1G12 A1G11 A1G10 1-12 00h 000B DTA1 EDT1 0 A1D21 A1D20 A1D13 A1D12 A1D11 A1D10 1-31 00h 000A HRA1 EHR1 0 A1H21 A1H20 A1H13 A1H12 A1H11 A1H10 0-23 00h 0009 MNA1 EMN1 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1M10 0-59 00h 0008 SCA1 ESC1 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A1S10 0-59 00h 0007 Alarm0 (NONVOLATILE) Y2K0 0 0 A0Y2K21 A0Y2K20 A0Y2K13 0 0 A0Y2K10 19/20 20h 0006 DWA0 EDW0 0 0 0 0 DY2 DY1 DY0 0-6 00h 0005 YRA0 Unused – Default = RTC Year value – Future expansion 0004 MOA0 EMO0 0 0 A0G20 A0G13 A0G12 A0G11 A0G10 1-12 00h 0003 DTA0 EDT0 0 A0D21 A0D20 A0D13 A0D12 A0D11 A0D10 1-31 00h 0002 HRA0 EHR0 0 A0H21 A0H20 A0H13 A0H12 A0H11 A0H10 0-23 00h 0001 MNA0 EMN0 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0M10 0-59 00h 0000 SCA0 ESC0 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11 A0S10 0-59 00h – Setting the Enable Month Bit (EMOn*) bit in combi- nation with other enable bits and a specific alarm time, the user can establish an alarm that triggers at the same time once a year. *n = 0 for Alarm 0: N = 1 for Alarm 1 When there is a match, an alarm flag is set. The occur- rence of an alarm can be determined by polling the AL0 and AL1 bits or by enabling the IRQ output, using it as hardware flag. The alarm enable bits are located in the MSB of the particular register. When all enable bits are set to ‘0’, there are no alarms. – The user can set the X1205 to alarm every Wednes- day at 8:00 AM by setting the EDWn*, the EHRn* and EMNn* enable bits to ‘1’ and setting the DWAn*, HRAn* and MNAn* Alarm registers to 8:00AM Wednesday. – A daily alarm for 9:30PM results when the EHRn* and EMNn* enable bits are set to ‘1’ and the HRAn* and MNAn* registers are set to 9:30PM. *n = 0 for Alarm 0: N = 1 for Alarm 1 |
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