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74ALVC32D Arkusz danych(PDF) 2 Page - NXP Semiconductors |
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74ALVC32D Arkusz danych(HTML) 2 Page - NXP Semiconductors |
2 / 13 page 74ALVC32_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 10 December 2007 2 of 13 NXP Semiconductors 74ALVC32 Quad 2-input OR gate 4. Functional diagram 5. Pinning information 5.1 Pinning Fig 1. Logic symbol Fig 2. IEC logic symbol mna242 1A 1B 1Y 2 1 3 2A 2B 2Y 5 4 6 3A 3B 3Y 10 9 8 4A 4B 4Y 13 12 11 mna243 3 ≥1 ≥1 ≥1 ≥1 2 1 6 5 4 8 10 9 11 13 12 Fig 3. Logic diagram (one gate) mna241 A B Y (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 32 1A VCC 1B 4B 1Y 4A 2A 4Y 2B 3B 2Y 3A GND 3Y 001aad101 1 2 3 4 5 6 7 8 10 9 12 11 14 13 001aad102 32 Transparent top view 2Y 3A 2B 3B 2A 4Y 1Y 4A 4B 1B GND(1) 6 9 5 10 4 11 3 12 2 13 terminal 1 index area |
Podobny numer części - 74ALVC32D |
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Podobny opis - 74ALVC32D |
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