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74AUP1T1326GT Arkusz danych(PDF) 3 Page - NXP Semiconductors |
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74AUP1T1326GT Arkusz danych(HTML) 3 Page - NXP Semiconductors |
3 / 24 page 74AUP1T1326_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 20 January 2009 3 of 24 NXP Semiconductors 74AUP1T1326 Low-power dual supply buffer/line driver; 3-state 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. Fig 2. Pin configuration SOT833-1 (XSON8) 74AUP1T1326 2OE 1Y 2Y 1OE VCC(A) A VCC(B) GND 001aaj294 36 27 18 45 Transparent top view Table 3. Pin description Symbol Pin Description VCC(B) 1 supply voltage B A 2 data input VCC(A) 3 supply voltage A GND 4 ground (0 V) 1OE 5 output enable input (Schmitt trigger input) 2OE 6 output enable input (Schmitt trigger input) 1Y 7 data output 2Y 8 data output Table 4. Function table[1] Input Output 1OE 2OE A 1Y 2Y LLX LZ XH L H L X HHHH HX L H L HX HHH |
Podobny numer części - 74AUP1T1326GT |
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Podobny opis - 74AUP1T1326GT |
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