74AUP2G80_4

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 04 — 2 June 2008

4 of 20

NXP Semiconductors

74AUP2G80

Low-power dual D-type flip-flop; positive-edge trigger

6.2 Pin description

7.

Functional description

[1]

H = HIGH voltage level;

L = LOW voltage level;

↑ = LOW-to-HIGH CP transition;

X = don’t care;

q = lower case letter indicates the state of referenced input, one setup time prior to the LOW-to-HIGH CP transition.

Fig 6.

Pin configuration SOT996-2 (XSON8U)

Fig 7.

Pin configuration SOT902-1 (XQFN8U)

001aai216

74AUP2G80

Transparent top view

8

7

6

5

1

2

3

4

1CP

1D

2Q

GND

1Q

2D

2CP

001aaf310

1D

2D

1CP

2CP

Transparent top view

3

6

1

5

7

2

terminal 1

index area

74AUP2G80

2Q

1Q

Table 3.

Pin description

Symbol

Pin

Description

SOT765-1, SOT833-1 and

SOT996-2

SOT902-1

1CP, 2CP

1, 5

7, 3

clock input

1D, 2D

2, 6

6, 2

data input

GND

4

4

ground (0 V)

1Q, 2Q

7, 3

1, 5

data output

8

8

supply voltage

Table 4.

Function table[1]

Input

Output

nCP

nD

nQ

↑

LH

↑

HL

LX

q