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74HCT164DB Arkusz danych(PDF) 10 Page - NXP Semiconductors |
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74HCT164DB Arkusz danych(HTML) 10 Page - NXP Semiconductors |
10 / 20 page 74HC_HCT164_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 2 February 2010 10 of 20 NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register (1) Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time 001aac427 MR input CP input Qn output tPHL tW frec VM VI GND VI VOH VOL GND VM VM (1) Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Waveforms showing the data set-up and hold times for Dn inputs 001aac428 GND GND th tsu th tsu VM VM VM VI VOH VOL VI Qn output CP input Dn input |
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